公开(公告)号：US09325341B2

公开(公告)日：2016-04-26

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM Incorporated

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M3/00 ,  H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。

公开(公告)号：US20220368299A1

公开(公告)日：2022-11-17

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/30 ,  H03M1/12 ,  H03F3/19 ,  H03F3/21

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain- stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US11294413B2

公开(公告)日：2022-04-05

申请号：US16835494

申请日：2020-03-31

Applicant: QUALCOMM Incorporated

Inventor： Balasubramanian Sivakumar ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Sean Baker ,  Liang Zhao

IPC: G05F3/08 ,  H04B1/16

Abstract: An apparatus for generating a substantially constant DC reference voltage. The apparatus includes a reference voltage generator configured to generate a substantially constant direct current (DC) reference voltage based on a voltage on a data signal transmission line, wherein the voltage is based on a bandgap reference voltage. In one implementation, the data signal transmission line is a differential signal transmission line and the voltage is a common mode voltage. In another implementation, the data signal transmission line is an I-data signal transmission line and a Q-data signal transmission line, and the voltage is an average or weighted-average of the common mode voltages of the I- and Q-differential signals. In another implementation, the reference voltage is based on a single-ended (e.g., positive- and/or negative)-component or vice-versa of I- and Q-data signals, respectively.

公开(公告)号：US11569801B2

公开(公告)日：2023-01-31

申请号：US17198515

申请日：2021-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

IPC: H03M1/00 ,  H03K3/356 ,  H03M3/00

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

公开(公告)号：US11870404B2

公开(公告)日：2024-01-09

申请号：US17320077

申请日：2021-05-13

Applicant: Qualcomm Incorporated

Inventor： Kentaro Yamamoto ,  Aram Akhavan ,  Ganesh Kiran ,  Lei Sun ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03G3/10 ,  H03G3/30 ,  H03F3/19 ,  H03F3/21 ,  H03M1/12

CPC classification number: H03G3/3036 ,  H03F3/19 ,  H03F3/21 ,  H03M1/124 ,  H03F2200/453

Abstract: An apparatus is disclosed for gain stabilization. In an example aspect, the apparatus includes an amplifier and a gain-stabilization circuit. The amplifier has a gain that is based on a bias voltage and an amplification control signal. The gain-stabilization circuit is coupled to the amplifier and includes a replica amplifier. The replica amplifier has a replica gain that is based on the bias voltage and the amplification control signal. The gain-stabilization circuit is configured to adjust at least one of the bias voltage or the amplification control signal based on a gain error associated with the replica amplifier.

公开(公告)号：US11476841B2

公开(公告)日：2022-10-18

申请号：US17198515

申请日：2021-03-11

Applicant: QUALCOMM INCORPORATED

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

IPC: H03M1/00 ,  H03K3/356 ,  H03M3/00

Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

公开(公告)号：US10044365B1

公开(公告)日：2018-08-07

申请号：US15843718

申请日：2017-12-15

Applicant: QUALCOMM Incorporated

Inventor： Liang Dai ,  Kentaro Yamamoto ,  Omid Rajaee ,  Li Lu ,  Dinesh Alladi ,  Changsok Han

IPC: H03M1/50 ,  H03L7/081 ,  H04W84/04 ,  H03M3/00

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

公开(公告)号：US09473165B2

公开(公告)日：2016-10-18

申请号：US14465650

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Sameer Wadhwa ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Xiaoke Wen ,  Masoud Ensafdaran ,  Weihua Chen

IPC: H03M1/66 ,  H03M1/72 ,  H03M1/80 ,  H03M1/06

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。

公开(公告)号：US20160065232A1

公开(公告)日：2016-03-03

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM INCORPORATED

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。

公开(公告)号：US11569837B1

公开(公告)日：2023-01-31

申请号：US17403683

申请日：2021-08-16

Applicant: QUALCOMM Incorporated

Inventor： Aram Akhavan ,  Kentaro Yamamoto ,  Lei Sun ,  Ganesh Kiran

IPC: H03M1/12 ,  H03M1/16 ,  H03F3/45

Abstract: Techniques and apparatus for output common-mode control of dynamic amplifiers, as well as analog-to-digital converters (ADCs) and other circuits implemented with such dynamic amplifiers. One example amplifier circuit includes a dynamic amplifier and a current source. The dynamic amplifier generally includes differential inputs, differential outputs, transconductance elements coupled to the differential inputs, a first set of capacitive elements coupled to the differential outputs, and a control input for controlling a time length of amplification for the dynamic amplifier. The current source is configured to generate an output current such that portions of the output current are selectively applied to the differential outputs of the dynamic amplifier during at least a portion of the time length of amplification.