Abstract:
A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.
Abstract:
A frequency source, such as for a wireless communications device, configured to have a duty cycle adjustment. A selected harmonic spur resulting from operation of the frequency source at one duty cycle may be avoided or minimized by operating the frequency source at a second duty cycle. Determination of the appropriate duty cycle may be based on measuring the amplitude of the harmonic spur as it appears in the output of a receive chain of the wireless device. Alternatively, the duty cycle may be set to desired value to avoid or minimize a given harmonic.
Abstract:
A frequency synthesizer is disclosed that includes an oscillator having an output to deliver a signal of a controllable frequency. The oscillator includes a capacitor bank responsive to an N-bit control signal to exhibit a capacitance. The oscillator output frequency is based on the capacitance. Control logic generates the N-bit control signal and determines each bit of the N-bit control signal through a binary search step and a modulation of a least-significant-bit (LSB) of the N-bit control signal. The LSB modulation, combined with the binary search for each bit, results in a higher accuracy frequency estimation.