公开(公告)号：US20140340132A1

公开(公告)日：2014-11-20

申请号：US13898215

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/1976 ,  H03L7/23

Abstract: A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

Abstract translation: 频率合成系统包括：时钟发生器，用于产生参考时钟信号;倍频器，用于响应于参考时钟信号的上升沿和下降沿产生倍频时钟信号;频率乘法器，用于产生倍频时钟 响应于倍频时钟信号的上升沿或下降沿的信号，以及耦合到倍频器的分数N合成器，以响应于倍频时钟信号而产生输出时钟信号。

公开(公告)号：US09112448B2

公开(公告)日：2015-08-18

申请号：US14065240

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03B5/36

CPC classification number: H03B5/362 ,  H03B5/364 ,  H03B2200/0046 ,  H03B2200/005 ,  H03B2200/0052 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract translation: 响应于模式信号，振荡器电路可以选择性地在正常模式和低功率模式之间切换。 在正常模式期间，振荡器电路可以采用第一放大器配置和第一容性负载来产生具有相对较低频率误差的高精度时钟信号。 在低功率模式期间，振荡器电路可采用第二放大器配置和第二容性负载，以使用最小功耗生成低功率时钟信号。 补偿电路可以用于在低功率模式期间抵消相对较高的频率误差。

公开(公告)号：US20150116051A1

公开(公告)日：2015-04-30

申请号：US14065240

申请日：2013-10-28

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03H9/24

CPC classification number: H03B5/362 ,  H03B5/364 ,  H03B2200/0046 ,  H03B2200/005 ,  H03B2200/0052 ,  H03B2200/0082 ,  H03B2201/0266

Abstract: An oscillator circuit may selectively switch between a normal mode and a low-power mode in response to a mode signal. During the normal mode, the oscillator circuit may employ a first amplifier configuration and a first capacitive loading to generate a high-accuracy clock signal having a relatively low frequency error. During the low power mode, the oscillator circuit may employ a second amplifier configuration and a second capacitive loading to generate a low-power clock signal using minimal power consumption. A compensation circuit may be used to offset a relatively high frequency error during the low-power mode.

Abstract translation: 响应于模式信号，振荡器电路可以选择性地在正常模式和低功率模式之间切换。 在正常模式期间，振荡器电路可以采用第一放大器配置和第一容性负载来产生具有相对较低频率误差的高精度时钟信号。 在低功率模式期间，振荡器电路可采用第二放大器配置和第二容性负载，以使用最小功耗生成低功率时钟信号。 补偿电路可以用于在低功率模式期间抵消相对较高的频率误差。

公开(公告)号：US08803575B2

公开(公告)日：2014-08-12

申请号：US13887888

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03L7/06

CPC classification number: H03L7/0893 ,  G11C7/222 ,  H03L7/099

Abstract: A charge pump circuit is disclosed that includes a main charge pump, a replica charge pump, and an op-amp. The main charge pump includes up and down input terminals to receive UP and DN control signals, a control terminal to receive a calibration signal, and an output to generate a control voltage. The replica charge pump includes up and down input terminals to receive DN and UP control signals, a control terminal to receive the calibration signal, and an output to generate a replica voltage. The op-amp generates the calibration signal in response to the control voltage and the replica voltage.

Abstract translation: 公开了一种电荷泵电路，其包括主电荷泵，复制电荷泵和运算放大器。 主电荷泵包括上下输入端子以接收UP和DN控制信号，控制端子接收校准信号，以及输出端产生控制电压。 复制电荷泵包括用于接收DN和UP控制信号的上下输入端子，用于接收校准信号的控制端子和用于产生复制电压的输出端。 运算放大器根据控制电压和复制电压产生校准信号。

公开(公告)号：US20160134312A1

公开(公告)日：2016-05-12

申请号：US14535928

申请日：2014-11-07

Applicant: QUALCOMM Incorporated

Inventor： Brian James Kaczynski ,  Emmanouil Terrovitis

IPC: H04B1/10 ,  H04B1/16 ,  H04B5/00

CPC classification number: H04B1/109 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/92 ,  H01L29/94 ,  H01L2924/0002 ,  H03H7/25 ,  H03H11/245 ,  H04B1/16 ,  H04B1/18 ,  H04B5/0012 ,  H04B5/0025 ,  H01L2924/00

Abstract: A variable attenuator can be used with high-voltage radio-frequency signals. The attenuator can provide wide dynamic range with little loss at the lowest attenuation level. The attenuator may be implemented in digital integrated circuit processes and occupies small integrated circuit area. Additionally, the use of circuit elements external to the SoC may be reduced. The attenuator uses multiple attenuator cells connected in parallel to an RF input and RF output. The attenuator cells use capacitive dividers with pair of capacitors laid out in the same integrated circuit area. The capacitors are also laid out so that the RF input shields the RF output from ground to avoid parasitic capacitance on the RF output.

Abstract translation: 可变衰减器可用于高压射频信号。 衰减器可以提供宽动态范围，在最低衰减水平下几乎没有损耗。 衰减器可以在数字集成电路工艺中实现并且占用小的集成电路区域。 另外，可以减少SoC外部的电路元件的使用。 衰减器使用与RF输入和RF输出并联连接的多个衰减器单元。 衰减器单元使用具有一对电容器的电容分压器，布置在同一集成电路区域中。 电容器也布置成使得RF输入屏蔽来自地面的RF输出，以避免RF输出端的寄生电容。

公开(公告)号：US08988121B2

公开(公告)日：2015-03-24

申请号：US13898215

申请日：2013-05-20

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03L7/06 ,  H03L7/08

CPC classification number: H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/1976 ,  H03L7/23

Abstract: A frequency synthesizing system includes a clock generator to generate a reference clock signal, a frequency doubler to generate a frequency-doubled clock signal in response to rising edges and falling edges of the reference clock signal, a frequency multiplier to generate a frequency-multiplied clock signal in response to either rising edges or falling edges of the frequency-doubled clock signal, and a fractional-N synthesizer coupled to the frequency multiplier to generate an output clock signal in response to the frequency-multiplied clock signal.

Abstract translation: 频率合成系统包括：时钟发生器，用于产生参考时钟信号;倍频器，用于响应于参考时钟信号的上升沿和下降沿产生倍频时钟信号;频率乘法器，用于产生倍频时钟 响应于倍频时钟信号的上升沿或下降沿的信号，以及耦合到倍频器的分数N合成器，以响应于倍频时钟信号而产生输出时钟信号。

公开(公告)号：US08536915B1

公开(公告)日：2013-09-17

申请号：US13651280

申请日：2012-10-12

Applicant: Qualcomm Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03L7/06

CPC classification number: H03L7/0891 ,  G11C7/222 ,  H03L7/099 ,  H03L7/16

Abstract: A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-controlled oscillator (VCO). The phase detector generates UP and DN control signals in response to a phase difference between a reference signal and a feedback signal. The charge pump generates a control voltage in response to the UP and DN control signals. The VCO adjusts the frequency of the output oscillation signal in response to the control voltage, generates the reference signal in response to the input oscillation signal, and generates the feedback signal in response to the output oscillation signal.

Abstract translation: 公开了延迟锁定环路（DLL）电路，其可以产生具有输入振荡信号的整数倍的频率的输出振荡信号。 该DLL包括相位检测器，电荷泵和压控振荡器（VCO）。 相位检测器响应于参考信号和反馈信号之间的相位差产生UP和DN控制信号。 电荷泵响应于UP和DN控制信号产生控制电压。 VCO根据控制电压调节输出振荡信号的频率，响应于输入振荡信号产生参考信号，并根据输出振荡信号产生反馈信号。

公开(公告)号：US08891725B2

公开(公告)日：2014-11-18

申请号：US13872367

申请日：2013-04-29

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis

IPC: H03K21/00 ,  H03L7/197 ,  H03K23/00

CPC classification number: H03K23/002 ,  H03L7/1976

Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

Abstract translation: 公开了一种分频器。 分频器包括多模预分频器，用于通过模M进行分频，其中M是N和2 * N-1之间的整数，N是2的幂。分频器还包括可编程计数器以输出 M的数字表示和输出时钟信号。 对于分频器，M等于N加D减去D \ N，对于多模预分频器输出时钟CKpr的每个边，其中计数器采样D的数字表示，D \ N表示D的整数部分除以N，以及 对于预分频器输出时钟CKpr的每个后续边沿，M等于N，其中计数器不对D的数字表示进行采样。

公开(公告)号：US08884707B2

公开(公告)日：2014-11-11

申请号：US13651340

申请日：2012-10-12

Applicant: QUALCOMM Incorporated

Inventor： Emmanouil Terrovitis ,  Abbas Komijani

IPC: H03K3/03

CPC classification number: H03K3/03 ,  H03K2005/00071

Abstract: An oscillator is disclosed that can generate an oscillation signal using a latch and two delay elements. For some embodiments, the oscillator includes an SR latch, a first delay element, and a second delay element. The SR latch has a first input, a second input, a first output, and a second output. The first delay element is coupled between the first output and the first input of the SR latch. The second delay element is coupled between the second output and the second input of the SR latch. For some embodiments, the first and second delay elements include a programmable pull-up circuit that allows the charging current to be adjusted in discrete amounts, and include a programmable capacitor circuit that allows the capacitance value to be adjusted in discrete amounts.

Abstract translation: 公开了一种使用锁存器和两个延迟元件产生振荡信号的振荡器。 对于一些实施例，振荡器包括SR锁存器，第一延迟元件和第二延迟元件。 SR锁存器具有第一输入，第二输入，第一输出和第二输出。 第一延迟元件耦合在第一输出和SR锁存器的第一输入端之间。 第二延迟元件耦合在SR锁存器的第二输出端和第二输入端之间。 对于一些实施例，第一和第二延迟元件包括允许以离散量调节充电电流的可编程上拉电路，并且包括允许以离散量调整电容值的可编程电容器电路。

公开(公告)号：US20140003570A1

公开(公告)日：2014-01-02

申请号：US13872367

申请日：2013-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Emmanouil Terrovitis

IPC: H03K23/00

CPC classification number: H03K23/002 ,  H03L7/1976

Abstract: A frequency divider is disclosed. The frequency divider includes a multi-modulus prescaler to perform a frequency division by a modulus M, wherein M is an integer between N and 2*N−1 and N is a power of 2. The frequency divider also includes a programmable counter to output the digital representation of M and an output clock signal. For the frequency divider, M equals N plus D minus D\N for each edge of the multi-modulus prescaler output clock CKpr wherein the counter samples the digital representation of D and D\N denotes an integer part of D divided by N, and M equals N for each subsequent edge of the prescaler output clock CKpr wherein the counter does not sample the digital representation of D.

Abstract translation: 公开了一种分频器。 分频器包括多模预分频器，用于通过模M进行分频，其中M是N和2 * N-1之间的整数，N是2的幂。分频器还包括可编程计数器以输出 M的数字表示和输出时钟信号。 对于分频器，M等于N加D减去D \ N，对于多模预分频器输出时钟CKpr的每个边，其中计数器采样D的数字表示，D \ N表示D的整数部分除以N，以及 对于预分频器输出时钟CKpr的每个后续边沿，M等于N，其中计数器不对D的数字表示进行采样。