公开(公告)号：US09754655B2

公开(公告)日：2017-09-05

申请号：US15340266

申请日：2016-11-01

Applicant: QUALCOMM Incorporated

Inventor： Mosaddiq Saifuddin ,  SankaraRao Kunapareddy ,  Keunsoo Roh ,  Chun Xiang He ,  Pratik Patel ,  Nicholas Ambur ,  Jeremy Haugen

IPC: G11C16/06 ,  G11C11/406 ,  G11C7/10 ,  G11C11/408 ,  G06F13/16 ,  G06F1/32

CPC classification number: G11C11/40615 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1636 ,  G11C7/1072 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.

公开(公告)号：US09690364B2

公开(公告)日：2017-06-27

申请号：US14846306

申请日：2015-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： Hee Jun Park ,  Haw-Jing Lo ,  Keunsoo Roh

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3275 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.