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公开(公告)号：US09991875B2
公开(公告)日：2018-06-05
申请号：US15352402
申请日：2016-11-15
Applicant: QUALCOMM Incorporated
Inventor： Timothy Donald Gathman , Ojas Choksi , Aleksandar Miodrag Tasic , Sasha Vujcic , Chirag Dipak Patel , Wu-Hsin Chen , Klaas Van Zalinge
CPC classification number: H03H11/0427 , H03F3/19 , H03F2200/294 , H03F2200/451 , H03H11/126 , H03H2011/0483 , H03H2011/0488 , H04B1/0053 , H04B1/1036 , H04L5/0041 , H04W88/08
Abstract: A reconfigurable filter circuit has a first path including a transimpedance amplifier (TIA). The transimpedance amplifier has an input that receives an input current and an output that outputs a voltage. The reconfigurable filter circuit also includes a switchable feedback path. The switchable feedback path includes a first low-pass filter coupled to an output of the TIA. The switchable feedback path also includes a first switch to couple the feedback path to provide a feedback current to the first path resulting in a bandpass response in the output voltage when the switch is closed and a low-pass response in the output voltage when the switch is open.
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公开(公告)号：US09379722B2
公开(公告)日：2016-06-28
申请号：US13926631
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Sriramgopal Sridhara , Li Liu
CPC classification number: H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.
Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。
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公开(公告)号：US10014845B2
公开(公告)日：2018-07-03
申请号：US15472055
申请日：2017-03-28
Applicant: QUALCOMM INCORPORATED
Inventor： Timothy Donald Gathman , Chirag Dipak Patel , Sasha Vujcic , Aleksandar Miodrag Tasic , Wu-Hsin Chen , Klaas van Zalinge
CPC classification number: H03H11/32 , H03F1/086 , H03F1/3205 , H03F1/3217 , H03F1/3223 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/3022 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2200/129 , H03F2200/144 , H03F2200/18 , H03F2200/21 , H03F2200/24 , H03F2200/294 , H03F2200/321 , H03F2200/33 , H03F2200/42 , H03F2200/451 , H03F2200/453 , H03F2200/555 , H03F2203/30069 , H03F2203/45091 , H03F2203/45101 , H03F2203/45116 , H03F2203/45136 , H03F2203/45208 , H03F2203/45288 , H03F2203/45374 , H03F2203/45458 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45596 , H03F2203/45712 , H04L7/0337
Abstract: A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.
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公开(公告)号：US20180048294A1
公开(公告)日：2018-02-15
申请号：US15472055
申请日：2017-03-28
Applicant: QUALCOMM INCORPORATED
Inventor： Timothy Donald Gathman , Chirag Dipak Patel , Sasha Vujcic , Aleksandar Miodrag Tasic , Wu-Hsin Chen , Klaas van Zalinge
CPC classification number: H03H11/32 , H03F1/086 , H03F1/3205 , H03F1/3217 , H03F1/3223 , H03F3/19 , H03F3/193 , H03F3/21 , H03F3/3022 , H03F3/45183 , H03F3/45237 , H03F3/45475 , H03F2200/06 , H03F2200/09 , H03F2200/129 , H03F2200/144 , H03F2200/18 , H03F2200/21 , H03F2200/24 , H03F2200/294 , H03F2200/321 , H03F2200/33 , H03F2200/42 , H03F2200/451 , H03F2200/453 , H03F2200/555 , H03F2203/30069 , H03F2203/45091 , H03F2203/45101 , H03F2203/45116 , H03F2203/45136 , H03F2203/45208 , H03F2203/45288 , H03F2203/45374 , H03F2203/45458 , H03F2203/45526 , H03F2203/45528 , H03F2203/45544 , H03F2203/45596 , H03F2203/45712 , H04L7/0337
Abstract: A circuit includes an active balun having an RF signal input and having differential signal outputs, the active balun including a first pair of transistors coupled to the RF signal input, the first pair of transistors including a first transistor of a first type and a second transistor of a second type, wherein the first type and second type are complementary; and an intermodulation distortion (IMD) sink circuit having an operational amplifier (op amp) coupled between a first node and a second node, wherein the first transistor and second transistor are coupled in series between the first node and the second node.
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公开(公告)号：US20140375363A1
公开(公告)日：2014-12-25
申请号：US13926631
申请日：2013-06-25
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Sriramgopal Sridhara , Li Liu
IPC: H03L7/18
CPC classification number: H03L7/18 , H03K3/017 , H03K5/1565 , H03K21/08
Abstract: A frequency divider with duty cycle adjustment within a feedback loop is disclosed. In an exemplary design, an apparatus includes at least one divider circuit and at least one duty cycle adjustment circuit coupled in a feedback loop. The divider circuit(s) receive a clock signal at a first frequency and provide at least one divided signal at a second frequency, which is a fraction of the first frequency. The duty cycle adjustment circuit(s) adjust the duty cycle of the at least one divided signal and provide at least one duty cycle adjusted signal to the divider circuit(s). The divider circuit(s) may include first and second latches, and the duty cycle adjustment circuit(s) may include first and second duty cycle adjustment circuits. The first and second latches and the first and second duty cycle adjustment circuits may be coupled in a feedback loop and may perform divide-by-2.
Abstract translation: 公开了一种在反馈环路内进行占空比调节的分频器。 在示例性设计中，装置包括耦合在反馈回路中的至少一个除法器电路和至少一个占空比调整电路。 分频器电路以第一频率接收时钟信号，并以第二频率提供至少一个分频信号，该第二频率是第一频率的一部分。 占空比调整电路调整至少一个分频信号的占空比，并向分频器电路提供至少一个占空比调整信号。 分频器电路可以包括第一和第二锁存器，并且占空比调整电路可以包括第一和第二占空比调整电路。 第一和第二锁存器以及第一和第二占空比调整电路可以耦合在反馈回路中并且可以执行除以2。
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Patent Agency Ranking
公开(公告)号：US11025195B2
公开(公告)日：2021-06-01
申请号：US16375765
申请日：2019-04-04
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Rui Xu , Marco Vigilante , Li Liu , Xiaotie Wu
Abstract: In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.
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公开(公告)号：US09948239B2
公开(公告)日：2018-04-17
申请号：US15272124
申请日：2016-09-21
Applicant: QUALCOMM Incorporated
Inventor： Kiyong Choi , Yi Zeng , Hong Sun Kim , Sasha Vujcic , Chirag Dipak Patel , Aleksandar Miodrag Tasic , Timothy Donald Gathman , Wu-Hsin Chen , Klaas van Zalinge
CPC classification number: H03D7/1458 , H03D7/1441 , H03D7/1466 , H03F3/193 , H03F3/21 , H03F3/265 , H03F3/72 , H03F2200/09 , H03F2200/294 , H03F2200/451 , H03F2200/537 , H03F2200/541 , H03G3/3052 , H04B1/109 , H04W52/0209
Abstract: A method and apparatus are disclosed for a configurable mixer capable of operating in a linear, a legacy, and a low-power mode. In the linear mode, the configurable mixer is configured to operate as a double-balanced mixer to multiply a first differential signal by a second differential signal. In the legacy mode, the configurable mixer is configured to as a double-balanced mixer to multiply a differential signal by a single-ended signal. In the low-power mode, the configurable mixer is configured to operate as a single-balanced mixer to multiply a differential signal by a single-ended signal. The operating mode of the configurable mixer may be based, at least in part, on a mode control signal. In some embodiments, the configurable mixer may be included in an analog front end of a wireless communication device.
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8.发明申请公开(公告)号：US20150163747A1
公开(公告)日：2015-06-11
申请号：US14102646
申请日：2013-12-11
Applicant: QUALCOMM Incorporated
Inventor： Wu-Hsin Chen , Gary Lee Brown, JR. , Chuan Wang , Aleksandar Miodrag Tasic
CPC classification number: H04W52/0238 , H04B1/109 , H04B1/525 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y02D70/40
Abstract: A device includes a common gate buffer circuit configured to receive a communication signal, an interfering signal detector configured to provide a control signal indicative of the power level of an interfering signal present with the communication signal and a control circuit configured to control an amount of current flowing through the common gate buffer circuit based on the control signal.
Abstract translation: 一种设备包括被配置为接收通信信号的公共门缓冲器电路，被配置为提供表示与通信信号一起存在的干扰信号的功率电平的控制信号的干扰信号检测器，以及被配置为控制电流量的控制电路 基于控制信号流过公共门缓冲电路。
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公开(公告)号：US20140273901A1
公开(公告)日：2014-09-18
申请号：US13800846
申请日：2013-03-13
Applicant: QUALCOMM INCORPORATED
Inventor： Li Liu , Steven C. Ciccarelli , Shrenik Patel , Prasad Srinivasa Siva Gudem , Zixiang Yang , Frederic Bossu , Wu-Hsin Chen , Chiewcharn Narathong
IPC: H04W52/02
CPC classification number: H04W52/0238 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/146 , Y02D70/21 , Y02D70/24
Abstract: A method for reducing power consumption on a wireless communication device is described. The wireless communication device includes a first stage active filter and a second stage active filter. A condition measurement is obtained that includes a signal measurement condition. If it is determined that the condition measurement is above a threshold, the second stage active filter is bypassed.
Abstract translation: 描述了一种用于降低无线通信设备的功耗的方法。 无线通信装置包括第一级有源滤波器和第二级有源滤波器。 获得包括信号测量条件的条件测量。 如果确定条件测量高于阈值，则旁路第二级有源滤波器。
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公开(公告)号：US12255663B2
公开(公告)日：2025-03-18
申请号：US18185325
申请日：2023-03-16
Applicant: QUALCOMM Incorporated
Inventor： Masoud Moslehi Bajestan , Arpit Gupta , Wu-Hsin Chen , Vinod Panikkath
Abstract: In certain aspects, a system includes a voltage-controlled oscillator (VCO), a phase detector configured to receive a reference signal, a frequency divider coupled between an output of the VCO and the phase detector, a phase-to-current circuit coupled to an output of the phase detector, and a temperature circuit configured to output a temperature-dependent voltage. The system also includes a switching circuit configured to selectively couple the phase-to-current circuit to an input of the VCO and configured to selectively couple the temperature circuit to the input of the VCO.
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