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    DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER
    1.
    发明申请
    DUAL STAGE LOW NOISE AMPLIFIER FOR MULTIBAND RECEIVER 有权
    双级接收机的双级低噪声放大器

    公开(公告)号：US20160087587A1

    公开(公告)日：2016-03-24

    申请号：US14491833

    申请日：2014-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Chuan Wang ,  Dongling Pan ,  Wing Fat Andy Lau ,  Jorge Andres Garcia ,  Zixiang Yang

    IPC: H03F1/02 ,  H03F1/26 ,  H03F3/19

    CPC classification number: H03F3/195 ,  H03F1/0205 ,  H03F1/26 ,  H03F1/56 ,  H03F3/19 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2203/21109 ,  H04B1/005

    Abstract: A dual stage LNA for use in multiband receivers is disclosed. In an exemplary embodiment, an apparatus includes a plurality of first stage amplifiers having a plurality of first stage output ports, respectively, to output first stage amplified voltage mode signals. The apparatus also includes a plurality of second stage amplifiers having a plurality of second stage input ports, respectively, and second stage output ports to output amplified current mode signals. The apparatus also includes a switch apparatus having input terminals connected to the first stage output ports and output terminals connected to the second stage input ports, the switch apparatus to connect selected second stage input ports to selected first stage output ports.

    Abstract translation: 公开了一种用于多频带接收机的双级LNA。 在示例性实施例中，装置包括分别具有多个第一级输出端口的多个第一级放大器，用于输出第一级放大的电压模式信号。 该装置还包括分别具有多个第二级输入端口的多个第二级放大器和用于输出放大的电流模式信号的第二级输出端口。 该装置还包括具有连接到第一级输出端口的输入端子和连接到第二级输入端口的输出端子的开关装置，该开关装置将所选择的第二级输入端口连接到所选择的第一级输出端口。

    Devices and methods for reducing noise in digitally controlled oscillators
    2.
    发明授权
    Devices and methods for reducing noise in digitally controlled oscillators 有权
    用于降低数字控制振荡器噪声的装置和方法

    公开(公告)号：US09100026B2

    公开(公告)日：2015-08-04

    申请号：US13938727

    申请日：2013-07-10

    Applicant: QUALCOMM Incorporated

    Inventor： Gary John Ballantyne ,  Bo Sun ,  Yi Tang ,  Zixiang Yang ,  Masoud Ensafdaran

    IPC: H03L7/099 ,  H03B5/12 ,  H03J5/24

    CPC classification number: H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

    Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

    Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。

    DIVIDING A FREQUENCY BY 1.5 TO PRODUCE A QUADRATURE SIGNAL
    4.
    发明申请
    DIVIDING A FREQUENCY BY 1.5 TO PRODUCE A QUADRATURE SIGNAL 有权
    将频率乘以1.5来产生一个四分之一信号

    公开(公告)号：US20130135016A1

    公开(公告)日：2013-05-30

    申请号：US13653054

    申请日：2012-10-16

    Applicant: QUALCOMM Incorporated

    Inventor： Wingching Vincent Leung ,  Zixiang Yang

    IPC: H03B19/06 ,  H03B19/00

    CPC classification number: H03L7/16 ,  H03B19/14 ,  H03B27/00

    Abstract: An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at a second frequency. The second frequency is the first frequency divided by 3. The apparatus also includes precision phase rotation circuitry that receives the six-phase signal and produces an eight-phase signal. The apparatus also includes a doubler that receives the eight-phase signal and produces a quadrature signal. The quadrature signal has a third frequency that is the first frequency divided by 1.5.

    Abstract translation: 公开了一种用于将频率除以1.5以产生正交信号的装置。 该装置包括分频器，其接收具有第一频率和两相的差分输入信号，并以第二频率产生六相信号。 第二频率是第一频率除以3.该装置还包括接收六相信号并产生八相信号的精密相位旋转电路。 该装置还包括一个接收八相信号并产生正交信号的倍频器。 正交信号具有第一频率除以1.5的第三频率。

    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS
    5.
    发明申请
    DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS 有权
    用于减少数字控制振荡器噪声的装置和方法

    公开(公告)号：US20150015343A1

    公开(公告)日：2015-01-15

    申请号：US13938727

    申请日：2013-07-10

    Applicant: QUALCOMM Incorporated

    Inventor： Gary John Ballantyne ,  Bo Sun ,  Yi Tang ,  Zixiang Yang ,  Masoud Ensafdaran

    IPC: H03L7/099

    CPC classification number: H03L7/0991 ,  H03B5/1265 ,  H03B2200/0088 ,  H03B2201/025 ,  H03B2202/017 ,  H03J5/24 ,  H03J2200/10 ,  H03J2200/36 ,  H03L7/099 ,  H03L2207/50

    Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.

    Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。

    Dividing a frequency by 1.5 to produce a quadrature signal
    7.
    发明授权
    Dividing a frequency by 1.5 to produce a quadrature signal 有权
    将频率除以1.5以产生正交信号

    公开(公告)号：US08803568B2

    公开(公告)日：2014-08-12

    申请号：US13653054

    申请日：2012-10-16

    Applicant: QUALCOMM Incorporated

    Inventor： Wingching Vincent Leung ,  Zixiang Yang

    IPC: H03B19/06

    CPC classification number: H03L7/16 ,  H03B19/14 ,  H03B27/00

    Abstract: An apparatus for dividing a frequency by 1.5 to produce a quadrature signal is disclosed. The apparatus includes a divider that receives a differential input signal with a first frequency and two phases and creates a six-phase signal at a second frequency. The second frequency is the first frequency divided by 3. The apparatus also includes precision phase rotation circuitry that receives the six-phase signal and produces an eight-phase signal. The apparatus also includes a doubler that receives the eight-phase signal and produces a quadrature signal. The quadrature signal has a third frequency that is the first frequency divided by 1.5.

    Abstract translation: 公开了一种用于将频率除以1.5以产生正交信号的装置。 该装置包括分频器，其接收具有第一频率和两相的差分输入信号，并以第二频率产生六相信号。 第二频率是第一频率除以3.该装置还包括接收六相信号并产生八相信号的精密相位旋转电路。 该装置还包括一个接收八相信号并产生正交信号的倍频器。 正交信号具有第一频率除以1.5的第三频率。

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