CPU/GPU DCVS CO-OPTIMIZATION FOR REDUCING POWER CONSUMPTION IN GRAPHICS FRAME PROCESSING
    1.
    发明申请
    CPU/GPU DCVS CO-OPTIMIZATION FOR REDUCING POWER CONSUMPTION IN GRAPHICS FRAME PROCESSING 有权
    CPU / GPU DCVS CO-OPTIMIZATION,用于降低图形帧处理中的功耗

    公开(公告)号:US20150317762A1

    公开(公告)日:2015-11-05

    申请号:US14266685

    申请日:2014-04-30

    Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

    Abstract translation: 公开了用于使图形帧处理中的功率消耗最小化的系统,方法和计算机程序。 一种这样的方法包括:启动由中央处理单元(CPU)和图形处理单元(GPU)协同执行的图形帧处理; 接收CPU活动数据和GPU活动数据; 确定用于GPU和CPU的一组可用动态时钟和电压/频率缩放(DCVS)电平; 以及基于CPU和GPU活动数据,从可用DCVS级别中选择GPU DCVS级别和CPU DCVS级别的最佳组合,其在图形帧处理期间最小化CPU和GPU的组合功耗。

    SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS
    3.
    发明申请
    SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS 审中-公开
    基于存储器访问模式解决DRAM页面冲突的系统和方法

    公开(公告)号:US20150199134A1

    公开(公告)日:2015-07-16

    申请号:US14172173

    申请日:2014-02-04

    Abstract: Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device. One embodiment includes receiving memory access pattern data for at least one of a plurality of memory clients prior to a corresponding memory transaction with a DRAM memory device. Next, it is determined, based on the received memory access pattern data, that a future transaction of a first of the plurality of memory clients may create a future page conflict with a current transaction of a second of the plurality of memory clients. The future page conflict is then resolved by interleaving access to an associated bank in the DRAM memory device by the first and second memory clients according to the received memory access pattern data.

    Abstract translation: 公开了用于管理对DRAM存储器件的访问请求的系统,方法和计算机程序。 一个实施例包括在与DRAM存储器设备进行相应的存储器交易之前接收多个存储器客户端中的至少一个的存储器访问模式数据。 接下来,基于接收到的存储器访问模式数据确定多个存储器客户端中的第一个的未来事务可以与多个存储器客户端中的第二个存储器客户端的当前事务产生未来页面冲突。 然后通过根据接收到的存储器访问模式数据,通过第一和第二存储器客户端交错对DRAM存储器设备中的相关联存储体的访问来解决未来页冲突。

Patent Agency Ranking