公开(公告)号：US09640247B2

公开(公告)日：2017-05-02

申请号：US14597146

申请日：2015-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Junmou Zhang ,  Min Chen

IPC: G06F7/58 ,  G11C11/417 ,  G11C7/10

CPC classification number: G11C11/417 ,  G06F7/588 ,  G11C7/1006

Abstract: One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

公开(公告)号：US20160202953A1

公开(公告)日：2016-07-14

申请号：US14597146

申请日：2015-01-14

Applicant: QUALCOMM Incorporated

Inventor： Nan Chen ,  Junmou Zhang ,  Min Chen

IPC: G06F7/58 ,  G11C11/417

CPC classification number: G11C11/417 ,  G06F7/588 ,  G11C7/1006

Abstract: One feature pertains to a true random number generator that utilizes the settling time of a bit cell as an entropy source to generate random digital output values. The bit cell may be a static random access memory bit cell. The bit cell's settling time may be converted into a digital output using an analog to digital converter. A plurality of bit cells may serially couple to one another in a ring formation. The bit cell ring can then be enabled such that each bit cell of the plurality of bit cells achieves a settling value that activates the subsequent bit cell in the ring causing it to in turn reach a settling value, and so on. An output node of one of the bit cells in the ring can then be sampled using a flip-flop to generate a continuous stream of random bits.

Abstract translation: 一个特征涉及一个真正的随机数发生器，其利用位单元的建立时间作为熵源来产生随机数字输出值。 位单元可以是静态随机存取存储器位单元。 位单元的建立时间可以使用模数转换器转换成数字输出。 多个位单元可以以环形形式彼此串联耦合。 然后可以启用比特单元环，使得多个比特单元中的每个比特单元实现一个建立值，该建立值激活环中随后的比特单元，从而使得其依次达到一个稳定值，依此类推。 然后可以使用触发器对环中的一个比特单元的输出节点进行采样，以生成连续的随机比特流。

公开(公告)号：US11823962B2

公开(公告)日：2023-11-21

申请号：US17180652

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

IPC: H01L21/66 ,  G06F30/398

CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

公开(公告)号：US11533045B1

公开(公告)日：2022-12-20

申请号：US17652092

申请日：2022-02-22

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Min Chen ,  Jianguo Yao ,  Bin Yang

IPC: H03K3/017 ,  H03K5/134 ,  H03K5/00

Abstract: In certain aspects, a duty-cycle monitor includes a first oscillator, and a flop having a signal input, a clock input, and an output, wherein the signal input is coupled to an input of the duty-cycle monitor, and the clock input is coupled to the first oscillator. The duty-cycle monitor also includes a first counter having a count input, an enable input, and a count output, wherein the count input of the first counter is coupled to the first oscillator, and the enable input of the first counter is coupled to the output of the flop. The duty-cycle monitor also includes a second counter having a count input, an enable input, and a count output, wherein the count input of the second counter is coupled to the first oscillator, and the enable input of the second counter is coupled to the output of the flop.

公开(公告)号：US20180143853A1

公开(公告)日：2018-05-24

申请号：US15398864

申请日：2017-01-05

Applicant: QUALCOMM INCORPORATED

Inventor： Mehdi Saeidi ,  Niladri Mojumder ,  Min Chen ,  Rajat Mittal ,  Rajit Chandra

IPC: G06F9/48 ,  G06F9/445

CPC classification number: G06F9/44505 ,  G06F9/5027 ,  G06F9/5061

Abstract: A system includes a computer processor including N cores; and a plurality of device aging sensors, wherein each one of the plurality of device aging sensors is disposed within a respective core, the plurality of device aging sensors being configured to communicate core aging information with a core scheduler in the computer processor, wherein the core scheduler is configured to make a first set of M cores available to a thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a first time period in which the core aging information indicates that aging of the first set of M cores is below a threshold, and wherein the core scheduler is configured to make a second set of M cores available to the thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a second time period.

公开(公告)号：US11764762B1

公开(公告)日：2023-09-19

申请号：US17898332

申请日：2022-08-29

Applicant: QUALCOMM Incorporated

Inventor： Haoyu Xiong ,  Min Chen

IPC: H03K3/03 ,  H03K19/0944 ,  H03K3/354

CPC classification number: H03K3/0315 ,  H03K3/354 ,  H03K19/0944

Abstract: An integrated circuit (IC) including a first ring oscillator (RO) including a first set of cascaded stages, wherein each of the first set of cascaded stages comprises a first logic inverter, including: a first set of field effect transistors (FETs) coupled in parallel between a first voltage rail and a first intermediate node, wherein the first set of FETs include a set of gates coupled to an input of the first logic inverter; and a second set of FETs coupled in series between the first intermediate node and a second voltage rail, wherein the second set of FETs includes at least a first FET including a gate coupled to the input of the first logic inverter, and at least a second FET that is diode-connected in accordance with a first mode of operation.

公开(公告)号：US20180034452A1

公开(公告)日：2018-02-01

申请号：US15271007

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Shan Lu ,  Nan Chen ,  Min Chen

IPC: H03K5/156 ,  H03K21/02 ,  H03K3/03

CPC classification number: H03K5/1565 ,  G01R31/31725 ,  H03K3/0315 ,  H03K21/026

Abstract: Methods and systems for independently tracking NMOS device process variation and PMOS device process variation are described herein. In one embodiment, a method for tracking process variation includes measuring a frequency of an NMOS-based ring oscillator on a chip, and determining a threshold voltage or switching speed for NMOS transistors on the chip based on the measured frequency of the NMOS-based ring oscillator. The method also includes measuring a frequency of a PMOS-based ring oscillator on the chip, and determining a threshold voltage or switching speed for PMOS transistors on the chip based on the measured frequency of the PMOS-based ring oscillator.

公开(公告)号：US09484892B1

公开(公告)日：2016-11-01

申请号：US14850801

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Min Chen ,  Jasmin Smaila Ibrahimovic ,  Carlos Auyon ,  Sorin Adrian Dobre ,  Navid Toosizadeh ,  Nan Chen ,  Mohamed Waleed Allam

IPC: G01R31/317 ,  H03K3/011 ,  H03K3/012

CPC classification number: H03K3/011 ,  G01R31/2884 ,  G01R31/31727 ,  H03K3/012

Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Abstract translation: 集成电路通过使用老化传感器测量老化并根据测量的老化来控制电源电压来补偿电路老化。 老化传感器的操作环境可以设置为减少非老化对测量老化的影响。 例如，操作环境可以使用温度反转电压。 初始老化测量值与初始未老化测量值之差可以存储在集成电路上。 核心功率降低控制器可以使用测量的老化和存储的初始老化测量值来更新性能传感器目标值，然后使用更新的性能传感器目标值来执行自适应电压缩放。