公开(公告)号：US10591531B2

公开(公告)日：2020-03-17

申请号：US15177964

申请日：2016-06-09

申请人： QUALCOMM Incorporated

发明人： Rajit Chandra ,  Melika Roshandell ,  Niladri Mojumder

IPC分类号： G01R31/28

摘要： An apparatus is disclosed. The apparatus includes a circuit, a conductor interconnecting a portion of the circuit, and a processor configured to determine a temperature of the conductor and adjust at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The at least one parameter includes a lifetime estimate for the conductor. A method of operating an apparatus including a circuit and a conductor interconnecting a portion of the circuit is disclosed. The method includes determining a temperature of the conductor, and adjusting at least one parameter related to the conductor in response to the determined temperature rising above a threshold. The parameter includes a lifetime estimate for the conductor.

公开(公告)号：US09666481B2

公开(公告)日：2017-05-30

申请号：US15141198

申请日：2016-04-28

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02

CPC分类号： H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

公开(公告)号：US20180143853A1

公开(公告)日：2018-05-24

申请号：US15398864

申请日：2017-01-05

申请人： QUALCOMM INCORPORATED

发明人： Mehdi Saeidi ,  Niladri Mojumder ,  Min Chen ,  Rajat Mittal ,  Rajit Chandra

IPC分类号： G06F9/48 ,  G06F9/445

CPC分类号： G06F9/44505 ,  G06F9/5027 ,  G06F9/5061

摘要： A system includes a computer processor including N cores; and a plurality of device aging sensors, wherein each one of the plurality of device aging sensors is disposed within a respective core, the plurality of device aging sensors being configured to communicate core aging information with a core scheduler in the computer processor, wherein the core scheduler is configured to make a first set of M cores available to a thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a first time period in which the core aging information indicates that aging of the first set of M cores is below a threshold, and wherein the core scheduler is configured to make a second set of M cores available to the thread scheduler and remaining cores of the N cores unavailable to the thread scheduler in a second time period.

公开(公告)号：US09336864B2

公开(公告)日：2016-05-10

申请号：US14473974

申请日：2014-08-29

申请人： QUALCOMM Incorporated

发明人： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/405 ,  G11C11/409

CPC分类号： G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

摘要： A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

摘要翻译： 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

公开(公告)号：US20160064068A1

公开(公告)日：2016-03-03

申请号：US14473974

申请日：2014-08-29

申请人： QUALCOMM Incorporated

发明人： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

摘要： A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

摘要翻译： 静态随机存取存储器（SRAM）电路包括耦合到写入端口的写入端口和读取端口。 读端口包括读位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

公开(公告)号：US09349686B2

公开(公告)日：2016-05-24

申请号：US14206360

申请日：2014-03-12

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang ,  Niladri Mojumder ,  Mustafa Badaroglu

IPC分类号： H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L21/76879 ,  H01L21/02167 ,  H01L21/76829 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.

摘要翻译： 系统和方法涉及一种集成电路，其包括由具有比铜的平均自由路径更低的示例性材料形成的减小的高度M1金属线，用于集成电路的片上电路元件的局部布线，其中降低的高度 M1金属线低于由铜形成的常规M1金属线的最小允许或允许的高度。 用于形成还原高度M1金属线的示例性材料包括钨（W），钼（Mo）和钌（Ru），其中这些示例性材料还具有比铜更低的电容和更低的RC延迟，同时提供高电迁移可靠性。

公开(公告)号：US09318564B2

公开(公告)日：2016-04-19

申请号：US14281710

申请日：2014-05-19

申请人： QUALCOMM Incorporated

发明人： Niladri Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC分类号： H01L29/76 ,  H01L29/40 ,  H01L29/161 ,  H01L27/02 ,  H01L27/11

CPC分类号： H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

摘要： Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

摘要翻译： 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二相对侧对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。