公开(公告)号：US20170285998A1

公开(公告)日：2017-10-05

申请号：US15086943

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Priyankar MATHURIA ,  Rakesh Kumar SINHA ,  Gururaj SHAMANNA

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/106 ,  G11C8/12 ,  G11C11/419 ,  G11C2207/005

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a memory. The memory may include a first memory portion configured to store a first bit and generate a first data bit output. The first data bit output may be a function of the first bit when a first read enable is active. The memory may also include a second memory portion configured to store a second bit and generate a second data bit output. The second data bit output may be a function of the second bit when a second read enable is active. The memory may include a switch configured to select between the first and second bits for a read operation based on the first and second data bit outputs.

公开(公告)号：US20230396248A1

公开(公告)日：2023-12-07

申请号：US18336621

申请日：2023-06-16

Applicant: QUALCOMM Incorporated

Inventor： Abhinav MURALI ,  Pradeep Kumar SANA ,  Sajin MOHAMAD ,  Harikrishna CHINTARLAPALLI REDDY ,  Rakesh Kumar SINHA ,  Jibu VARGHESE K

IPC: H03K17/687 ,  H04B1/40

CPC classification number: H03K17/6872 ,  H04B1/40

Abstract: An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.

公开(公告)号：US20150063046A1

公开(公告)日：2015-03-05

申请号：US14018404

申请日：2013-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Kumar SINHA ,  Chirag GULATI ,  Ritu CHABA ,  Sei Seung YOON

IPC: G11C7/06 ,  G11C7/04

CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。