公开(公告)号：US20150161067A1

公开(公告)日：2015-06-11

申请号：US14099786

申请日：2013-12-06

Applicant: QUALCOMM Incorporated

Inventor： Kevin Robert BOWLES ,  Hari Madhava RAO ,  Sei Seung YOON

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4004 ,  G06F13/16 ,  Y02D10/14 ,  Y02D10/151

Abstract: A reduced-area interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce area and energy consumption. Tri-state buffers inserted into XBAR data paths are configured to direct data between clients and sources on a number of data paths corresponding to the lesser of the number of clients and the number of sources. Interface area and power consumption is reduced by eliminating paths that are not always being used.

Abstract translation: 缩小区域互连允许客户端使用XBAR架构进行客户端通信。 XBAR编译器生成具有XBAR数据路径的芯片设计，以减少面积和能耗。 插入到XBAR数据路径中的三态缓冲区被配置为在客户端和源之间的数据路径上指定与客户端数量和源数量相对应的数量较少的数据路径。 通过消除不总是使用的路径来减少接口面积和功耗。

公开(公告)号：US20150228314A1

公开(公告)日：2015-08-13

申请号：US14176705

申请日：2014-02-10

Applicant: QUALCOMM Incorporated

Inventor： Xiaoliang BAI ,  Arun Babu PALLERLA ,  Sei Seung YOON

IPC: G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1084 ,  G11C11/412 ,  G11C11/419

Abstract: A data latch includes a first stage configured to receive an input in a first voltage domain, and a second stage. The second stage includes a level shifter configured to shift the input from the first voltage domain to a second voltage domain, and an output circuit having a pull down circuit and pull up circuit arranged to generate an output in the second voltage domain, wherein the pull down circuit is responsive to the input in the first voltage domain and the pull up circuit is responsive to the input in the second voltage domain.

Abstract translation: 数据锁存器包括被配置为接收第一电压域中的输入的第一级和第二级。 第二级包括电平移位器，其被配置为将输入从第一电压域移位到第二电压域;以及输出电路，具有下拉电路和上拉电路，布置成在第二电压域中产生输出，其中拉 下拉电路响应于第一电压域中的输入，并且上拉电路响应于第二电压域中的输入。

公开(公告)号：US20150063046A1

公开(公告)日：2015-03-05

申请号：US14018404

申请日：2013-09-04

Applicant: QUALCOMM INCORPORATED

Inventor： Rakesh Kumar SINHA ,  Chirag GULATI ,  Ritu CHABA ,  Sei Seung YOON

IPC: G11C7/06 ,  G11C7/04

CPC classification number: G11C7/06 ,  G11C7/04 ,  G11C7/08 ,  G11C7/227

Abstract: Disclosed are various apparatuses and methods for a memory with a multiple word line design. A memory timing circuit may include a dummy word line including a first portion and a second portion and further including capacitative loading that is lumped in the second portion of the dummy word line, a first transistor connected to the first portion of the dummy word line and configured to charge the dummy word line, and a second transistor connected to the second portion of the dummy word line and configured to discharge the dummy word line. A method may include charging a dummy word line using a first transistor, and discharging the dummy word line using a second transistor, wherein the dummy word line includes a first portion and a second portion and further includes capacitative loading that is lumped in the second portion of the dummy word line.

Abstract translation: 公开了具有多字线设计的存储器的各种装置和方法。 存储器定时电路可以包括包括第一部分和第二部分的虚拟字线，并且还包括集中在伪字线的第二部分中的电容负载，连接到虚拟字线的第一部分的第一晶体管和 被配置为对所述虚拟字线充电;以及第二晶体管，连接到所述虚拟字线的第二部分，并且被配置为对所述虚拟字线进行放电。 一种方法可以包括使用第一晶体管对虚拟字线进行充电，以及使用第二晶体管对该虚拟字线进行放电，其中，所述虚拟字线包括第一部分和第二部分，并且还包括集中在所述第二部分中的电容负载 的虚拟字线。

公开(公告)号：US20180068714A1

公开(公告)日：2018-03-08

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin LIANG ,  Tony Chung Yiu KWOK ,  Rui LI ,  Sei Seung YOON

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：US20150085568A1

公开(公告)日：2015-03-26

申请号：US14038434

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chirag GULATI ,  Rakesh SINHA ,  Ritu CHABA ,  Sei Seung YOON

IPC: G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract translation: 集成电路包括一个或多个位单元，耦合到所述一个或多个位单元的字线以及与所述字线布置以在其间具有电容的虚拟字线。 该电容提供了字线的升压或降压以辅助读和写操作。

公开(公告)号：US20150067290A1

公开(公告)日：2015-03-05

申请号：US14018399

申请日：2013-09-04

Applicant: QUALCOMM Incorporated

Inventor： Ritu CHABA ,  Balachander GANESAN ,  ChangHo JUNG ,  Sei Seung YOON

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G06F2212/1028

Abstract: Disclosed are various apparatuses and methods for memory access time tracking in dual-rail systems. An apparatus may include a memory coupled to a first voltage rail and having a data output, a data circuit coupled to a second voltage rail and configured to receive the data output from the memory, and a timing circuit configured to adjust an access time of the memory based on a second voltage rail level. A method may include determining a voltage rail level of a data circuit, adjusting the access time of the memory based on the voltage rail level of the data circuit, outputting data from the memory, and receiving the output data by the data circuit.

Abstract translation: 公开了用于双轨系统中的存储器访问时间跟踪的各种装置和方法。 设备可以包括耦合到第一电压轨并具有数据输出的存储器，耦合到第二电压轨并被配置为接收从存储器输出的数据的数据电路，以及定时电路，被配置为调整存储器的访问时间 基于第二电压轨级的存储器。 一种方法可以包括确定数据电路的电压轨级，基于数据电路的电压轨电平调整存储器的访问时间，从存储器输出数据，以及由数据电路接收输出数据。

公开(公告)号：US20190095295A1

公开(公告)日：2019-03-28

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad AHMED ,  Chulmin JUNG ,  Sei Seung YOON ,  Esin TERZIOGLU

IPC: G06F11/20

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US20170221551A1

公开(公告)日：2017-08-03

申请号：US15013897

申请日：2016-02-02

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  Fahad AHMED ,  Sei Seung YOON ,  Keejong KIM

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C7/02 ,  G11C5/06 ,  G11C7/00 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C29/02 ,  G11C29/026 ,  G11C29/14 ,  G11C29/50012

Abstract: A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

公开(公告)号：US20160055903A1

公开(公告)日：2016-02-25

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung YOON ,  Tony Chung Yiu KWOK ,  Changho JUNG ,  Nishith Nitin DESAI

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

公开(公告)号：US20150279452A1

公开(公告)日：2015-10-01

申请号：US14228091

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung YOON ,  Derek Xiaoxiang Yang ,  Alex Dongkyu Park ,  Venkatasubramanian Narayanan

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1057 ,  G11C2207/005

Abstract: A memory and a method for operating the memory having a precharge circuit with inputs of multiple voltage domains are provided. In one aspect, a memory includes a bitline and one or more storage elements coupled to the bitline. The one or more storage elements are configured to operate in a first voltage domain using a first supply voltage. A pull-up circuit is configured to pull up the bitline to a second supply voltage in a second voltage domain. The pull-up circuit is responsive to a first control signal in the first voltage domain and a second control signal in the second voltage domain. The first supply voltage is different than the second supply voltage.

Abstract translation: 提供一种用于操作具有具有多个电压域的输入的预充电电路的存储器的存储器和方法。 在一个方面，存储器包括位线和耦合到位线的一个或多个存储元件。 一个或多个存储元件被配置为使用第一电源电压在第一电压域中操作。 上拉电路被配置为在第二电压域中将位线上拉到第二电源电压。 上拉电路响应于第一电压域中的第一控制信号和第二电压域中的第二控制信号。 第一电源电压不同于第二电源电压。