公开(公告)号：US11184018B1

公开(公告)日：2021-11-23

申请号：US17087234

申请日：2020-11-02

Applicant: QUALCOMM Incorporated

Inventor： Xilin Liu ,  Parisa Mahmoudidaryan ,  Shahin Mehdizad Taleie ,  Negar Rashidi ,  Dongwon Seo

IPC: H03M1/18 ,  H03M1/82 ,  H03M1/06 ,  H03M1/10 ,  H03K5/156 ,  H03K5/05 ,  H03M1/80 ,  H03K5/00

Abstract: Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.

公开(公告)号：US11705921B2

公开(公告)日：2023-07-18

申请号：US17337619

申请日：2021-06-03

Applicant: QUALCOMM Incorporated

Inventor： Xilin Liu ,  Nitz Saputra ,  Behnam Sedighi ,  Ashok Swaminathan ,  Dongwon Seo

IPC: H03M1/66 ,  H03M1/74 ,  H04B1/04 ,  G05F3/26 ,  H03M1/00 ,  H03M1/68

CPC classification number: H03M1/74 ,  G05F3/262 ,  H04B1/04 ,  H03M1/002 ,  H03M1/68

Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.

公开(公告)号：US10516412B1

公开(公告)日：2019-12-24

申请号：US16138499

申请日：2018-09-21

Applicant: QUALCOMM INCORPORATED

Inventor： Shahin Mehdizad Taleie ,  Ashok Swaminathan ,  Sudharsan Kanagaraj ,  Negar Rashidi ,  Siyu Yang ,  Behnam Sedighi ,  Honghao Ji ,  Jaswinder Singh ,  Andrew Weil ,  Dongwon Seo ,  Xilin Liu

IPC: H03M1/66 ,  G04F10/00 ,  H03M1/68

Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.