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公开(公告)号:US11196434B1
公开(公告)日:2021-12-07
申请号:US17062193
申请日:2020-10-02
Applicant: QUALCOMM Incorporated
Inventor: Lei Sun , Honghao Ji , Dan Yuan
Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.
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公开(公告)号:US09705307B2
公开(公告)日:2017-07-11
申请号:US14606746
申请日:2015-01-27
Applicant: QUALCOMM Incorporated
Inventor: Honghao Ji , Dongwon Seo
CPC classification number: H02H3/18 , H01L27/0266 , H01L27/0292 , H02H11/003
Abstract: A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.
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3.
公开(公告)号:US20200099389A1
公开(公告)日:2020-03-26
申请号:US16367712
申请日:2019-03-28
Applicant: QUALCOMM Incorporated
Inventor: Eunyung Sung , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Honghao Ji , Shahin Mehdizad Taleie , Dongwon Seo
Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.
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公开(公告)号:US20160218499A1
公开(公告)日:2016-07-28
申请号:US14606746
申请日:2015-01-27
Applicant: QUALCOMM Incorporated
Inventor: Honghao Ji , Dongwon Seo
IPC: H02H3/18
CPC classification number: H02H3/18 , H01L27/0266 , H01L27/0292 , H02H11/003
Abstract: A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.
Abstract translation: 提供了一个反向电流保护(RCP)电路,其包括耦合在电源轨和缓冲电源节点之间的RCP开关。 由缓冲器电源节点上的缓冲器电源供电的控制电路控制RCP开关响应于在电源轨上承载的电源电压的放电而打开。
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公开(公告)号:US10797720B2
公开(公告)日:2020-10-06
申请号:US16367712
申请日:2019-03-28
Applicant: QUALCOMM Incorporated
Inventor: Eunyung Sung , Nitz Saputra , Behnam Sedighi , Ashok Swaminathan , Honghao Ji , Shahin Mehdizad Taleie , Dongwon Seo
Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.
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6.
公开(公告)号:US09379727B1
公开(公告)日:2016-06-28
申请号:US14628996
申请日:2015-02-23
Applicant: QUALCOMM Incorporated
Inventor: Dongwon Seo , Yang You , Honghao Ji , Tongyu Song , Ganesh Saripalli , Shahin Mehdizad Taleie
IPC: H03M1/06 , H03M1/70 , H04B1/04 , G05F3/18 , G05F1/56 , H03M1/00 , H03M1/74 , G05F1/575 , H02M3/156
CPC classification number: H03M1/0604 , G05F1/56 , G05F1/575 , G05F3/18 , H02M3/156 , H03F3/24 , H03M1/00 , H03M1/70 , H03M1/747 , H04B1/0475 , H04B2001/0408
Abstract: A method and apparatus for attenuating transmit digital to analog converter (DAC) spurs is provided. The method begins when a reference voltage is injected into an amplifier. Next, an output of the ground low drop-out regulator is measured and is them compared with the reference voltage. The output of the amplifier is then adjusted based on the results of the comparison. If the reference voltage is higher then the output of the ground low drop-out regulator the output of the amplifier is adjusted to ground. If the reference voltage is lower than the output of the ground low drop-out regulator then the output of the amplifier is adjusted to match the reference voltage.
Abstract translation: 提供了用于衰减发射数模转换器(DAC)杂散的方法和装置。 当将参考电压注入放大器时,该方法开始。 接下来,测量接地低压降稳压器的输出,并将其与参考电压进行比较。 然后根据比较结果调整放大器的输出。 如果参考电压较高,则接地低压降稳压器的输出将放大器的输出调整到地。 如果参考电压低于接地低压降稳压器的输出,则调节放大器的输出以匹配参考电压。
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公开(公告)号:US10516412B1
公开(公告)日:2019-12-24
申请号:US16138499
申请日:2018-09-21
Applicant: QUALCOMM INCORPORATED
Inventor: Shahin Mehdizad Taleie , Ashok Swaminathan , Sudharsan Kanagaraj , Negar Rashidi , Siyu Yang , Behnam Sedighi , Honghao Ji , Jaswinder Singh , Andrew Weil , Dongwon Seo , Xilin Liu
Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.
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公开(公告)号:US10305361B2
公开(公告)日:2019-05-28
申请号:US15710704
申请日:2017-09-20
Applicant: QUALCOMM Incorporated
Inventor: Nitz Saputra , Sang Min Lee , Dongwon Seo , Vinay Kundur , Behnam Sedighi , Honghao Ji
Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.
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