Successive approximation register (SAR) analog-to-digital converter (ADC) with noise-shaping property

    公开(公告)号:US11196434B1

    公开(公告)日:2021-12-07

    申请号:US17062193

    申请日:2020-10-02

    Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node; a digital filter configured to apply a filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

    SELF-SENSING REVERSE CURRENT PROTECTION SWITCH
    4.
    发明申请
    SELF-SENSING REVERSE CURRENT PROTECTION SWITCH 有权
    自感式反向电流保护开关

    公开(公告)号:US20160218499A1

    公开(公告)日:2016-07-28

    申请号:US14606746

    申请日:2015-01-27

    CPC classification number: H02H3/18 H01L27/0266 H01L27/0292 H02H11/003

    Abstract: A reverse current protection (RCP) circuit is provided that includes an RCP switch coupled between a power supply rail and a buffer power supply node. A control circuit powered by a buffer supply voltage on the buffer power supply node controls the RCP switch to open in response to a discharge of a power supply voltage carried on the power supply rail.

    Abstract translation: 提供了一个反向电流保护(RCP)电路,其包括耦合在电源轨和缓冲电源节点之间的RCP开关。 由缓冲器电源节点上的缓冲器电源供电的控制电路控制RCP开关响应于在电源轨上承载的电源电压的放电而打开。

    Low voltage input calibrating digital to analog converter

    公开(公告)号:US10305361B2

    公开(公告)日:2019-05-28

    申请号:US15710704

    申请日:2017-09-20

    Abstract: A calibrating digital to analog converter (calDAC) architecture uses a low voltage memory to store the digital inputs of calDACs. The calDAC architecture includes a low voltage domain and a high voltage domain coupled to the low voltage domain. The low voltage domain includes a calDAC memory and a finite state machine (FSM). The high voltage domain includes a calDAC core, an interface circuit, and a bias control circuit coupled to the interface circuit. The interface circuit may be provided between the calDAC core and the low voltage domain. The bias control circuit is coupled to the interface circuit to generate a bias voltage for the interface circuit to drive switch transistors of the calDAC core.

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