公开(公告)号：US09692396B2

公开(公告)日：2017-06-27

申请号：US14711158

申请日：2015-05-13

Applicant: QUALCOMM Incorporated

Inventor： Xinxin Yu ,  Ashok Swaminathan ,  Christian Venerus

IPC: H03K3/03 ,  H03K3/011 ,  H03L7/099

CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03L7/0995 ,  H03L7/0997

Abstract: A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.

公开(公告)号：US10862461B1

公开(公告)日：2020-12-08

申请号：US16431943

申请日：2019-06-05

Applicant: QUALCOMM Incorporated

Inventor： Tonmoy Biswas ,  Sreenivasa Mallia ,  Krishnaswamy Thiagarajan ,  Ashok Swaminathan ,  Vinod Panikkath

IPC: G06F1/04 ,  H03K3/00 ,  H03K3/037 ,  H03K5/13 ,  H04B1/40 ,  H03K5/00 ,  H03K19/20

Abstract: Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

公开(公告)号：US12113499B2

公开(公告)日：2024-10-08

申请号：US18068837

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Peter Gazzerro ,  Nitz Saputra ,  Ashok Swaminathan ,  Osama Elhadidy ,  Bo Yang

IPC: H03H11/04 ,  H03M1/06 ,  H03M1/66 ,  H04B1/04

CPC classification number: H03H11/0461 ,  H03M1/0626 ,  H03M1/66 ,  H04B1/04

Abstract: Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

公开(公告)号：US10516412B1

公开(公告)日：2019-12-24

申请号：US16138499

申请日：2018-09-21

Applicant: QUALCOMM INCORPORATED

Inventor： Shahin Mehdizad Taleie ,  Ashok Swaminathan ,  Sudharsan Kanagaraj ,  Negar Rashidi ,  Siyu Yang ,  Behnam Sedighi ,  Honghao Ji ,  Jaswinder Singh ,  Andrew Weil ,  Dongwon Seo ,  Xilin Liu

IPC: H03M1/66 ,  G04F10/00 ,  H03M1/68

Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

公开(公告)号：US09680391B2

公开(公告)日：2017-06-13

申请号：US14670996

申请日：2015-03-27

Applicant: QUALCOMM Incorporated

Inventor： Christian Venerus ,  Ashok Swaminathan

IPC: H02M7/217 ,  G01R19/00 ,  G01R19/165 ,  G06F1/26 ,  H03K19/003 ,  H02M1/00

CPC classification number: H02M7/217 ,  G01R19/0084 ,  G01R19/165 ,  G01R19/16547 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  H02M2001/0025 ,  H03K19/00346 ,  Y02D10/126

Abstract: A droop detector includes: a plurality of input nodes, each input node configured to receive a supply voltage; an output node; a plurality of detector modules, each detector module comprises: an input terminal coupled to each input node, an output terminal coupled to the output node; and an input tracking unit configured as a voltage follower to detect a droop in the supply voltage coupled to each input node and output an output voltage that follows the supply voltage on the output terminal when the droop is detected on the supply voltage; and a comparator coupled to the output node and configured to output a control signal when the droop is detected.

公开(公告)号：US20170005665A1

公开(公告)日：2017-01-05

申请号：US14789095

申请日：2015-07-01

Applicant: QUALCOMM Incorporated

Inventor： Ashok Swaminathan ,  Christian Venerus ,  Marzio Pedrali-Noy

IPC: H03L7/099

CPC classification number: H03L7/099 ,  H03B5/04 ,  H03B2202/042 ,  H03B2202/06 ,  H03L1/00

Abstract: Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.

Abstract translation: 公开了用于提供电压变化补偿的方法，系统和电路。 一种系统包括：电压比较器，配置成响应于检测到一个或多个电源电压下降到阈值以下，来控制控制信号; 锁相环（PLL），被配置为响应于所述控制信号的断言来分频所述PLL的输出频率; 对应于多个电源电压的多个电压传感器，所述电压传感器被配置为输出表示其相应电源电压的电压电平的各个数字信号; 以及控制电路，被配置为响应于各个数字信号在开环模式期间控制PLL中的振荡器频率。

公开(公告)号：US09054687B2

公开(公告)日：2015-06-09

申请号：US13954277

申请日：2013-07-30

Applicant: QUALCOMM Incorporated

Inventor： Ashok Swaminathan ,  Ian Galton

IPC: H03K3/282 ,  H03K3/354

CPC classification number: H03K3/354 ,  H03B5/24

Abstract: An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes a second current source, and a pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source. The proposed oscillating circuit generates an output signal which has a linear gain over a wide tuning range.

Abstract translation: 提出了一种具有线性增益的振荡电路。 振荡电路可以包括张弛振荡器和电流补偿模块。 张弛振荡器包括电容器，一对电阻器，用于向电容器传送第一电流;以及第一电流源，适于产生具有第一预定电平的第一电流。 电流补偿块包括第二电流源和耦合到第二电流源的一对交叉耦合晶体管，并且适于将稳定在振荡器中的第一预定电平的电流从电容器转移到第二电流源。 所提出的振荡电路产生在宽的调谐范围内具有线性增益的输出信号。

公开(公告)号：US12040817B2

公开(公告)日：2024-07-16

申请号：US17659531

申请日：2022-04-18

Applicant: QUALCOMM Incorporated

Inventor： Nitz Saputra ,  Ashok Swaminathan

IPC: H03M1/78 ,  H03K17/687 ,  H03M1/76

CPC classification number: H03M1/785 ,  H03K17/687 ,  H03M1/76

Abstract: Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

公开(公告)号：US11990911B2

公开(公告)日：2024-05-21

申请号：US17654916

申请日：2022-03-15

Applicant: QUALCOMM Incorporated

Inventor： Negar Rashidi ,  Nitz Saputra ,  Ashok Swaminathan

IPC: H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M1/82

CPC classification number: H03K5/05 ,  G06F1/08 ,  H03K5/156 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215 ,  H03M1/82

Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

公开(公告)号：US11705921B2

公开(公告)日：2023-07-18

申请号：US17337619

申请日：2021-06-03

Applicant: QUALCOMM Incorporated

Inventor： Xilin Liu ,  Nitz Saputra ,  Behnam Sedighi ,  Ashok Swaminathan ,  Dongwon Seo

IPC: H03M1/66 ,  H03M1/74 ,  H04B1/04 ,  G05F3/26 ,  H03M1/00 ,  H03M1/68

CPC classification number: H03M1/74 ,  G05F3/262 ,  H04B1/04 ,  H03M1/002 ,  H03M1/68

Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.