公开(公告)号：US20220021389A1

公开(公告)日：2022-01-20

申请号：US16930151

申请日：2020-07-15

申请人： QUALCOMM Incorporated

发明人： Narender PONNA ,  Sharad Kumar GUPTA ,  Akhtar ALAM

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K19/017

摘要： According to certain aspects, a level shifter includes a first branch including a first pull-up transistor configured to pull up a first node, and a first pull-down transistor configured to pull down the first node. The level shifter also includes a second branch including a second pull-up transistor configured to pull up a second node, and a second pull-down transistor configured to pull down the second node. The level shifter further includes a third branch including a third pull-up transistor configured to pull up a third node, and a third pull-down transistor configured to pull down the third node. The first branch is cross coupled with the third branch, the second branch is cross coupled with the third branch, the first pull-down transistor has a first channel width, the second pull-down transistor has a second channel width, and the first channel width is greater than the second channel width.

公开(公告)号：US20240249056A1

公开(公告)日：2024-07-25

申请号：US18156999

申请日：2023-01-19

申请人： QUALCOMM Incorporated

发明人： Hyeokjin LIM ,  Ankur MEHROTRA ,  Renukprasad HIREMATH ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Akhtar ALAM ,  Kamesh MEDISETTI ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC分类号： G06F30/392 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528 ,  H01L27/02

CPC分类号： G06F30/392 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5286 ,  H01L27/0207

摘要： A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.

公开(公告)号：US20240088014A1

公开(公告)日：2024-03-14

申请号：US17940911

申请日：2022-09-08

申请人： QUALCOMM Incorporated

发明人： Keyurkumar Karsanbhai KANSAGRA ,  Manjanaika CHANDRANAIKA ,  Ankit GUPTA ,  Kamesh MEDISETTI ,  Akhtar ALAM

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5223 ,  H01L23/5221 ,  H01L23/5286

摘要： In certain aspects, a chip includes first source/drain contacts formed over a first oxide diffusion (OD), and first gates, wherein each of the first gates is disposed between a respective pair of the first source/drain contacts. The chip also includes a first bridge coupling a first one of the first source/drain contacts, a first one of the first gates, and a second one of the first source/drain contacts. The chip also includes a first metal routing coupled to the first one of the first source/drain contacts, and a second metal routing coupled to the second one of the first source/drain contacts.