公开(公告)号：US20240266342A1

公开(公告)日：2024-08-08

申请号：US18165259

申请日：2023-02-06

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Hyeokjin LIM ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: H01L27/02 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392

Abstract: A chip includes a first column including first rails extending in a first direction, the first rails having a first pitch. The chip also includes a second column including second rails extending in the first direction, the second rails having a second pitch different from the first pitch. The chip also includes a transition region between the first column and the second column.

公开(公告)号：US20240249056A1

公开(公告)日：2024-07-25

申请号：US18156999

申请日：2023-01-19

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Ankur MEHROTRA ,  Renukprasad HIREMATH ,  Foua VANG ,  Manjanaika CHANDRANAIKA ,  Akhtar ALAM ,  Kamesh MEDISETTI ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI

IPC: G06F30/392 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5286 ,  H01L27/0207

Abstract: A chip includes a spare cell including a first active region, and a first gate extending over the first active region in a first direction. The chip also includes a tie cell including a second active region, a second gate extending over the second active region in the first direction, a first drain contact formed over the second active region, a first source contact formed over the second active region, wherein the second gate is between the first drain contact and the first source contact, and first source contact is coupled to a first rail, and a circuit configured to couple the second gate to a second rail. The chip also includes a metal routing extending in a second direction, wherein the second direction is perpendicular to the first direction, and the first metal routing is coupled to the first drain contact and the first gate.

公开(公告)号：US20240170488A1

公开(公告)日：2024-05-23

申请号：US17993594

申请日：2022-11-23

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad HIREMATH ,  Keyurkumar Karsanbhai KANSAGRA ,  Shashikumar GANESH BHAT ,  Hyeokjin LIM ,  Seung Hyuk KANG ,  Venugopal BOYNAPALLI ,  Kamesh MEDISETTI

IPC: H01L27/118 ,  H03K19/094

CPC classification number: H01L27/11807 ,  H03K19/094 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: An integrated circuit (IC) cell including: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in a cell row direction; and a source region, common to the first and second logic gates, situated between the first and second polysilicon structures, wherein the first and second pins are on a first metal track directly over the common source region.

公开(公告)号：US20190252408A1

公开(公告)日：2019-08-15

申请号：US15895094

申请日：2018-02-13

Applicant: QUALCOMM Incorporated

Inventor： Hyeokjin LIM ,  Xiangdong CHEN ,  Renukprasad HIREMATH ,  Rui LI ,  Venugopal BOYNAPALLI

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/092 ,  H01L2027/11816 ,  H01L2027/11855 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A semiconductor die includes a first diffusion region and a plurality of gates extending across the diffusion region. The plurality of gates are substantially parallel to each other. An interconnect layer above the diffusion region and plurality of gates includes a plurality of signal traces extending in a direction substantially perpendicular to the gates. At least two of the plurality of signal traces are located directly above the diffusion region such that at intersections of two gates with two separate signal traces are in the active transistor region, that is the portion of the gate extending over the diffusion region. Gate contacts coupling the two gates to the two separate signal traces are staggered by coupling to different signal traces.