公开(公告)号：US20170077963A1

公开(公告)日：2017-03-16

申请号：US14852988

申请日：2015-09-14

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook JUNG ,  Sara CHOI ,  Byungkyu SONG ,  Taehui NA ,  Jisu KIM ,  Jung Pill KIM ,  Sungryul KIM ,  Taehyun KIM ,  Seung Hyuk KANG

IPC: H03M13/00

CPC classification number: H03M13/616 ,  G06F11/10 ,  G06F11/1012 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/617 ,  H03M13/6502

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract translation: 错误检测和校正解码装置根据数据输入是否包含单位错误或多位错误，执行单错误纠正双重错误检测（SEC-DED）或双重纠错三重错误检测（DEC-TED） ，以减少单位错误时的功耗和延迟，并在多位错误的情况下提供强大的纠错。

公开(公告)号：US20160093350A1

公开(公告)日：2016-03-31

申请号：US14499153

申请日：2014-09-27

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook JUNG ,  Taehui NA ,  Byungkyu SONG ,  Jung Pill KIM ,  Seung Hyuk KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1675 ,  G11C2207/002

Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.

Abstract translation: 系统和方法涉及使用多阶段配置的电路的磁阻随机存取存储器（MRAM）位单元的操作。 在感测电路阶段中，电路被配置为确定位单元两端的数据电压与参考电压之间的第一差分电压。 在预放大阶段，电路被配置为对第一差分电压进行预放大，以产生预放大的差分电压，其不会由于工艺变化而产生偏移电压。 在读出放大器相位中，电路被配置为在锁存器中放大预放大的差分电压。 预放大的差分电压的产生可消除锁存器中可能出现的偏移电压。 在写入阶段，电路还被配置为将写数据值写入MRAM位单元。