公开(公告)号：US20190097640A1

公开(公告)日：2019-03-28

申请号：US15714372

申请日：2017-09-25

Applicant: QUALCOMM Incorporated

Inventor： Karthik Nagarajan ,  Chenling Huang ,  Debesh Bhatta

IPC: H03L7/093 ,  H03L7/089 ,  H03K5/1252 ,  H03K5/26

CPC classification number: H03L7/093 ,  H03K5/1252 ,  H03K5/26 ,  H03K2005/00013 ,  H03L7/07 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/22 ,  H03L7/235

Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.

公开(公告)号：US09425755B1

公开(公告)日：2016-08-23

申请号：US14812054

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Jingxue Lu ,  Chenling Huang

IPC: H05K1/18 ,  H03F3/45 ,  H03F3/217

CPC classification number: H03F3/45668 ,  H03F3/2171 ,  H03F3/24 ,  H03F3/245 ,  H03F3/45497 ,  H03F2203/45151 ,  H03F2203/45522 ,  H03F2203/45526 ,  H04B2001/0408

Abstract: A differential class-D amplifier module having common-mode swing limiter circuit is disclosed. The differential class-D amplifier module may include differential class-D amplifier configured to generate differential pulse width modulated (PWM) output signals based on differential input signals and at least a portion of the differential PWM output signals that are fed back to the differential class-D amplifier. The common-mode swing limiter circuit may attenuate one or more common-mode signal components associated with the PWM output signals that may be fed back to input terminals of the differential class-D amplifier.

Abstract translation: 公开了具有共模摆幅限幅器电路的差分D类放大器模块。 差分D类放大器模块可以包括差分D类放大器，其被配置为基于差分输入信号产生差分脉冲宽度调制（PWM）输出信号，以及反馈到差分类的至少一部分差分PWM输出信号 -D放大器。 共模摆幅限制器电路可以衰减与可以反馈到差分D类放大器的输入端的PWM输出信号相关联的一个或多个共模信号分量。

公开(公告)号：US11616505B1

公开(公告)日：2023-03-28

申请号：US17674666

申请日：2022-02-17

Applicant: QUALCOMM Incorporated

Inventor： Sungmin Ock ,  Chenling Huang

IPC: H03K17/14 ,  H03K17/16 ,  H03H11/04 ,  H04M1/02 ,  H03K3/03 ,  H03F3/45

Abstract: A temperature-compensated low-pass filter includes a differential amplifier that controls a first transistor to pass a subthreshold current through the transistor to charge a capacitor with low-pass-filtered output voltage. A second transistor has a first terminal coupled to an input terminal of the low-pass filter and has a second terminal coupled to a current source conducting a bias current. The differential amplifier also controls the second transistor to conduct the bias current responsive to a difference between a complementary-to-absolute-temperature reference voltage and a voltage of the second terminal of the second transistor.

公开(公告)号：US10411718B2

公开(公告)日：2019-09-10

申请号：US15714372

申请日：2017-09-25

Applicant: QUALCOMM Incorporated

Inventor： Karthik Nagarajan ,  Chenling Huang ,  Debesh Bhatta

IPC: H03L7/06 ,  H03L7/093 ,  H03L7/089 ,  H03K5/26 ,  H03K5/1252 ,  H03L7/07 ,  H03L7/087 ,  H03L7/22 ,  H03L7/23 ,  H03K5/00

Abstract: A method and apparatus for reducing the amount of jitter in a signal are disclosed. In one embodiment a feed-forward loop compares the edges of a reference clock and an input signal, converts a time difference of the compared edges into a voltage signal, and controls a time delay in a voltage controlled delay line in order to reduce or eliminate jitter.