公开(公告)号：US20140281405A1

公开(公告)日：2014-09-18

申请号：US13841576

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Daren Eugene Streett ,  Brian Michael Stempel ,  Thomas Philip Speier ,  Rodney Wayne Smith ,  Michael Scott McIlvaine ,  Kenneth Alan Dockser ,  James Norris Dieffenderfer

IPC: G06F9/30

CPC classification number: G06F9/30098 ,  G06F9/30189 ,  G06F9/3842 ,  G06F9/3863

Abstract: A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.

Abstract translation: 处理器包括用于存储在寄存器字段的当前值的上下文中处理的指令的队列，其中对于一些实施例，取决于处理时的寄存器字段，指令是未定义的或定义的。 在执行写入指令（写入寄存器字段的指令）之后，将搜索包含依赖于执行的写入指令的指令的任何条目。 每个这样的条目存储处理条目中的指令时的寄存器字段的值。 如果在队列中找到这样的条目，并且其寄存器字段的存储值与写入指令写入寄存器字段的值不匹配，则处理器刷新流水线并在一个状态下重新启动，以便正确地执行指令 。

公开(公告)号：US09514061B1

公开(公告)日：2016-12-06

申请号：US14716947

申请日：2015-05-20

Applicant: QUALCOMM Incorporated

Inventor： Henry Arthur Pellerin, III ,  Thomas Philip Speier ,  Thomas Andrew Sartorius ,  Michael William Morrow ,  James Norris Dieffenderfer ,  Kenneth Alan Dockser ,  Michael Scott McIlvaine

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/0895 ,  G06F2212/1016 ,  G06F2212/401 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory structure compresses a portion of a memory tag using an indexed tag compression structure. A set of higher order bits of the memory tag may be stored in the indexed tag compression structure, where the set of higher order bits are identified by an index value. A tag array stores a set of lower order bits of the memory tag and the index value identifying the entry in the tag compression structure storing the set of higher order bits of the memory tag. The memory tag may comprise at least a portion of a memory address of a data element stored in a data array.

Abstract translation: 存储器结构使用索引标签压缩结构压缩存储器标签的一部分。 存储器标签的一组较高位可以存储在索引标签压缩结构中，其中较高位的集合由索引值标识。 标签阵列存储存储器标签的一组较低位，以及标识在存储标签的较高位的集合的标签压缩结构中的条目的索引值。 存储器标签可以包括存储在数据阵列中的数据元素的存储器地址的至少一部分。

公开(公告)号：US20210091928A1

公开(公告)日：2021-03-25

申请号：US17029394

申请日：2020-09-23

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Alan Dockser

IPC: H04L9/06 ,  H04L9/08

Abstract: A key-schedule cache stores at least one key schedule based on a cipher key for data transformation using a block cipher. To obtain the round key for a data transformation, a key-word set, which may be a cipher key, including at least one round key is received in a round key control-circuit. The round key control-circuit determines whether the plurality of key words is already stored in the key-schedule cache and also determines whether the next round key, based on the key-word set, is also stored in the key-schedule cache. If the next round key is stored in the key-schedule cache, the round key control-circuit reads the next round key from the key-schedule cache and supplies the next round key to a next round key output. The round key control-circuit may also generate the next round key.

公开(公告)号：US09823929B2

公开(公告)日：2017-11-21

申请号：US13841576

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Daren Eugene Streett ,  Brian Michael Stempel ,  Thomas Philip Speier ,  Rodney Wayne Smith ,  Michael Scott McIlvaine ,  Kenneth Alan Dockser ,  James Norris Dieffenderfer

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/30189 ,  G06F9/3842 ,  G06F9/3863

Abstract: A processor includes a queue for storing instructions processed within the context of a current value of a register field, where for some embodiments the instruction is undefined or defined, depending upon the register field at time of processing. After a write instruction (an instruction that writes to the register field) executes, the queue is searched for any entries that contain instructions that depend upon the executed write instruction. Each such entry stores the value of the register field at the time the instruction in the entry was processed. If such an entry is found in the queue and its stored value of the register field does not match the value that the write instruction wrote to the register field, then the processor flushes the pipeline and restarts at a state so as to correctly execute the instruction.

公开(公告)号：US09471325B2

公开(公告)日：2016-10-18

申请号：US14091340

申请日：2013-11-27

Applicant: QUALCOMM Incorporated

Inventor： Anil Krishna ,  Sandeep Suresh Navada ,  Niket Kumar Choudhary ,  Michael Scott McIlvaine ,  Thomas Andrew Sartorius ,  Rodney Wayne Smith ,  Kenneth Alan Dockser

IPC: G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3861

Abstract: A method and apparatus for allowing an out-of-order processor to reuse an in-use physical register is disclosed herein. The method and apparatus uses identifiers, such as tokens and/or other identifiers in a rename map table (RMT) and a physical register file (PRF), to indicate whether an instruction result is allowed or disallowed to be written into a physical register.

Abstract translation: 本文公开了一种允许无序处理器重用使用中物理寄存器的方法和装置。 该方法和装置使用诸如重命名映射表（RMT）和物理寄存器文件（PRF）中的令牌和/或其他标识符的标识符来指示是否允许或不允许将指令结果写入物理寄存器。

公开(公告)号：US09753694B2

公开(公告)日：2017-09-05

申请号：US14692071

申请日：2015-04-21

Applicant: QUALCOMM Incorporated

Inventor： Kenneth Alan Dockser ,  Michael Thomas Dibrino ,  Pathik Sunil Lall

IPC: G06F7/537 ,  G06F7/535 ,  G06F5/01 ,  G06F7/487

CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F7/4873 ,  G06F7/5375 ,  G06F2205/003 ,  G06F2207/535

Abstract: Systems and methods relate to division of a dividend by a divisor, with fast result formatting. Counts of leading sign bits of the dividend and the divisor are determined. The dividend and the divisor are normalized based on their respective counts of leading sign bits to obtain a normalized dividend and a normalized divisor, respectively. An exact number of significant quotient bits of a quotient of the division, based on the normalized dividend, the normalized divisor, and the counts of leading sign bits of the dividend and the divisor and used to determine a correct position of a leading bit of the quotient based on this exact number. The quotient is developed by placing the leading bit at or near the correct position and appending less significant bits to the right of the leading bit. Thus, left-shifts in each iteration and large final shifts are avoided in formatting the result.

公开(公告)号：US20130218938A1

公开(公告)日：2013-08-22

申请号：US13768698

申请日：2013-02-15

Applicant: Qualcomm Incorporated

Inventor： Kenneth Alan Dockser ,  Pathik Sunil Lall

IPC: G06F7/485

CPC classification number: G06F7/485

Abstract: Provided are a floating-point adder and methods for implementing a floating-point adder with operand shifting based on a predicted exponent difference when performing an effective subtraction on normal or subnormal numbers. In an aspect, two least significant bits (LSBs) of a first floating-point operand's exponent are compared with two LSBs of a second floating-point operand's exponent to estimate a difference between the two exponents. A first shift of up to one of the first and the second operands is performed, based on the estimated difference. A prospective result is then produced by subtracting the first operand and the second operand. Contemporaneously, one of the first operand's exponent and the second operand's exponent is subtracted from the other of the first operand's exponent and the second operand's exponent to determine if the exponents actually differ by one or less. If the first operand's exponent and the second operand's exponent differ by one or less, the prospective result is provided as the raw difference of the operands.

Abstract translation: 提供了一种浮点加法器和用于在对正常或正常数进行有效减法时基于预测指数差来实现具有操作数移位的浮点加法器的方法。 在一方面，将第一浮点运算数的指数的两个最低有效位（LSB）与第二浮点运算指数的两个LSB进行比较，以估计两个指数之间的差。 基于估计的差异，执行高达第一和第二操作数之一的第一移位。 然后通过减去第一操作数和第二操作数产生预期结果。 同时，第一个操作数的指数和第二个操作数的指数之一从第一个操作数的指数和第二个操作数的指数的另一个中减去，以确定指数实际上是否相差一个或更少。 如果第一个操作数的指数和第二个操作数的指数相差一个或多个，则预期结果作为操作数的原始差异提供。