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公开(公告)号：US10019021B1
公开(公告)日：2018-07-10
申请号：US15712488
申请日：2017-09-22
Applicant: Qualcomm Incorporated
Inventor： Gordon Lee , Marko Koski , Zdravko Lukic
Abstract: The present disclosure describes aspects of voltage settling detection for switching regulators. In some aspects, an integrated circuit for controlling a switching regulator includes a modulator having an output coupled to switch drive circuitry of the switching regulator. A digital-to-analog converter (DAC) has a first output coupled to an input of the modulator and a second output configured to indicate when a digital-to-analog conversion is complete. A voltage settling detector is configured to receive, from the second output of DAC, an indication that the digital-to-analog conversion is complete and detect a signal transition at the output of the modulator. Based on the indication and the signal transition, the voltage settling detector can provide a status indication for the switching regulator. By so doing, the voltage settling detector may indicate that an output voltage of the switching regulator is proximate a target output voltage level set by the DAC.
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公开(公告)号：US11159009B2
公开(公告)日：2021-10-26
申请号：US14151725
申请日：2014-01-09
Applicant: QUALCOMM Incorporated
Inventor： Marko Koski
Abstract: Exemplary embodiments are related to a buck regulator. A buck regulator may include an inductor selectively coupled to an output and a power supply. The regulator may also include a controller configured to detect an over-current event if an amount of current flowing from the power supply to the inductor is equal to or greater than a current threshold and detect a low-voltage event if a voltage at the output is less than or equal to a reference voltage. Further, in response to the over-current event and the low-voltage event, the controller may be configured to prevent current from flowing from the power supply to the inductor until substantially all energy stored by the inductor has been dissipated.
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公开(公告)号：US10715122B2
公开(公告)日：2020-07-14
申请号：US15966939
申请日：2018-04-30
Applicant: Qualcomm Incorporated
Inventor： Guolei Yu , Ajay Kumar Kosaraju , Marko Koski
Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
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公开(公告)号：US20190334512A1
公开(公告)日：2019-10-31
申请号：US15966939
申请日：2018-04-30
Applicant: Qualcomm Incorporated
Inventor： Guolei Yu , Ajay Kumar Kosaraju , Marko Koski
Abstract: An apparatus is disclosed that includes a voltage-controlled delay generator. In an example aspect, the apparatus includes voltage-controlled timing circuitry, duty cycle detection circuitry, and output circuitry. The voltage-controlled timing circuitry is configured to receive a control voltage. The voltage-controlled timing circuitry includes a current source, a control transistor, and a capacitor that are configured to produce a voltage indicator based on the control voltage. The duty cycle detection circuitry is coupled to the voltage-controlled timing circuitry. The duty cycle detection circuitry is configured to detect the voltage indicator and provide a duty cycle indicator based on the voltage indicator. The output circuitry is coupled to the duty cycle detection circuitry and is configured to generate a duty signal based on the duty cycle indicator.
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公开(公告)号：US10439597B1
公开(公告)日：2019-10-08
申请号：US15953157
申请日：2018-04-13
Applicant: Qualcomm Incorporated
Inventor： Guolei Yu , Ajay Kumar Kosaraju , Charles Tuten , Marko Koski , Aniruddha Bashar
Abstract: The present disclosure provides a duty locked loop circuit that includes a switch network including a first electronic switch device controlled by a first control signal that is based on a first input signal and a second electronic switch device controlled by a second control signal that is based on a second input signal. The duty locked loop circuit includes an integrator circuit electrically connected to the switch network. The integrator circuit is configured to generate an output voltage proportional to an integral of a difference between a first duty cycle of the first input signal and a second duty cycle of the second input signal. The duty locked loop circuit includes an output circuit configured to generate an output signal having an output duty cycle that is based on the output voltage.
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Patent Agency Ranking
公开(公告)号：US20190089244A1
公开(公告)日：2019-03-21
申请号：US15708379
申请日：2017-09-19
Applicant: Qualcomm Incorporated
Inventor： Marko Koski , Charles Tuten
Abstract: The present disclosure describes aspects of power regulation with charge pumps. In some aspects, an integrated circuit (IC) includes multiple processor cores and a power input connected to an internal power rail of the IC. The IC may also comprise embedded charge pumps coupled between the internal power rail of the IC and respective input power rails of the multiple processor cores. Capacitors of the embedded charge pumps may be implemented with on-die capacitors suitable for integration with a die of the circuit to facilitate the embedding of the charge pumps. Alternately or additionally, separate input power rails of the processor cores and the embedded charge pumps may enable more-efficient power regulation or power management on a per-processor core basis, such as when a processor core is throttled or idled to reduce power consumption.
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公开(公告)号：US12130648B2
公开(公告)日：2024-10-29
申请号：US18302734
申请日：2023-04-18
Applicant: QUALCOMM Incorporated
Inventor： Marko Koski , Edgar Marti-Arbona , Gordon Lee , Anish Muttreja , Ravi Jenkal
CPC classification number: G05F1/5735 , G05F1/562 , H02M1/0009 , H02M1/0025
Abstract: A method and apparatuses for power regulation using an extended current limit are disclosed. The power regulator detects an occurrence of an output current of the regulator exceeding a first current limit, triggers an extended current limit timer based on the detected occurrence, regulates the output current according to a second current limit higher than the first current limit based on a duration of the extended current limit timer, and regulates the output current according to the first current limit based on an expiration of the duration of the extended current limit timer.
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公开(公告)号：US20220360159A1
公开(公告)日：2022-11-10
申请号：US17315444
申请日：2021-05-10
Applicant: Qualcomm Incorporated
Inventor： Troy Lynn Stockstad , Yi-Cheng Wan , Marko Koski , Ajay Kumar Kosaraju
Abstract: An apparatus is disclosed for harvesting ringing energy. In an example aspect, the apparatus includes a bootstrap circuit. The bootstrap circuit includes a bootstrap capacitor and a bootstrap switch. The bootstrap switch includes a first terminal configured to accept an input voltage. The bootstrap switch also includes a second terminal coupled to the bootstrap capacitor. The bootstrap switch additionally includes a body diode comprising an anode coupled to the first terminal and a cathode coupled to the second terminal. The bootstrap switch is configured to be in an open state to charge the bootstrap capacitor via the body diode. The bootstrap switch is also configured to provide a voltage at the second terminal of the bootstrap switch. The voltage is greater than an average of the input voltage.
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公开(公告)号：US10707753B2
公开(公告)日：2020-07-07
申请号：US15708379
申请日：2017-09-19
Applicant: Qualcomm Incorporated
Inventor： Marko Koski , Charles Tuten
Abstract: The present disclosure describes aspects of power regulation with charge pumps. In some aspects, an integrated circuit (IC) includes multiple processor cores and a power input connected to an internal power rail of the IC. The IC may also comprise embedded charge pumps coupled between the internal power rail of the IC and respective input power rails of the multiple processor cores. Capacitors of the embedded charge pumps may be implemented with on-die capacitors suitable for integration with a die of the circuit to facilitate the embedding of the charge pumps. Alternately or additionally, separate input power rails of the processor cores and the embedded charge pumps may enable more-efficient power regulation or power management on a per-processor core basis, such as when a processor core is throttled or idled to reduce power consumption.
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10.发明授权公开(公告)号：US12107497B2
公开(公告)日：2024-10-01
申请号：US17370689
申请日：2021-07-08
Applicant: QUALCOMM Incorporated
Inventor： Chris Rosolowski , Todd Sutton , Orlando Santiago , Joseph Duncan , Rashed Hoque , Marko Koski , Zdravko Lukic
Abstract: A voltage regulator circuit using predictively precharged voltage rails is generally disclosed. For example, the voltage regulator circuit may include a main switching regulator configured to provide a target voltage, the main switching regulator having a first voltage node, a precharge switching regulator configured to provide a precharge voltage, the precharge switching regulator having a second voltage node, the precharge voltage based on a difference between the target voltage and a next target voltage to be provided by the main switching regulator, and a precharge switch circuit configured to selectively couple the second voltage node to an output voltage node based upon a transition from the target voltage to the next target voltage.
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