公开(公告)号：US09762228B2

公开(公告)日：2017-09-12

申请号：US14855238

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Neha Agrawal ,  Sajin Mohamad ,  Chulkyu Lee

IPC: H03K21/00 ,  H03K7/06 ,  H03K19/21 ,  H03K3/037 ,  H03K21/10 ,  H03K23/64 ,  H03K23/00 ,  H03K21/02 ,  G06F1/08

CPC classification number: H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

公开(公告)号：US20170077918A1

公开(公告)日：2017-03-16

申请号：US14855238

申请日：2015-09-15

Applicant: QUALCOMM Incorporated

Inventor： Neha Agrawal ,  Sajin Mohamad ,  Chulkyu Lee

IPC: H03K7/06 ,  H03K3/037 ,  H03K19/21

CPC classification number: H03K7/06 ,  G06F1/08 ,  H03K3/037 ,  H03K19/21 ,  H03K21/00 ,  H03K21/026 ,  H03K21/10 ,  H03K23/00 ,  H03K23/64

Abstract: Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.

Abstract translation: 通过可编程分频比对输入时钟信号进行分频的系统和方法可以产生输出时钟信号，输出时钟信号与输入时钟信号的延迟无关于分频比的值，输出时钟信号的占空比为50 ％独立于分频比的值。 示例性可编程时钟分频器包括模N计数器，其产生计数分频比的计数信号和产生公共半速率时钟信号的半速率时钟信号发生器，偶数半速率时钟信号和奇数 半速率时钟信号以输出时钟信号的一半速率切换。 公共半速时钟信号，偶数半速率时钟信号和奇数半速率时钟信号被组合以产生输出时钟信号。