公开(公告)号：US10522236B2

公开(公告)日：2019-12-31

申请号：US15081640

申请日：2016-03-25

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman ,  Vaishnavi Sundaralingam ,  Madhura Hegde ,  Nikhil Sudhakaran

IPC分类号： G11C29/12 ,  G06F3/06 ,  G06F11/07 ,  G11C17/16 ,  G11C17/18 ,  G11C29/44 ,  G11C29/00

摘要： A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

公开(公告)号：US11455221B2

公开(公告)日：2022-09-27

申请号：US17025133

申请日：2020-09-18

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman

IPC分类号： G06F11/07 ,  G06F11/20 ,  G11C29/38 ,  H03K19/02

摘要： A memory includes an error detection circuit that identifies a faulty feature in an array of memory cells within the memory. A redundancy enable circuit functions to replace the faulty feature with a redundant feature. The error detection circuit and the redundancy enable circuit function concurrently with a read operation on the array of memory cells.

公开(公告)号：US20180259578A1

公开(公告)日：2018-09-13

申请号：US15862554

申请日：2018-01-04

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman

IPC分类号： G01R31/317 ,  G01R31/3187 ,  G01R31/3185

CPC分类号： G01R31/31724 ,  G01R31/31707 ,  G01R31/31727 ,  G01R31/318563 ,  G01R31/3187 ,  G06F2201/83

摘要： A BIST circuit is provided with modes of operation in which the BIST procedure for a circuit-under-test occurs at a system clock rate for the circuit-under-test that is greater than a test clock rate for the BIST circuit.

公开(公告)号：US09711241B2

公开(公告)日：2017-07-18

申请号：US14676501

申请日：2015-04-01

申请人： QUALCOMM Incorporated

发明人： Ashutosh Anand ,  Shankarnarayan Bhat ,  Nikhil Sudhakaran ,  Praveen Raghuraman ,  Nishi Bhushan Singh ,  Anand Bhat ,  Abhinav Kothiala ,  Sanjay Muchini ,  Arun Balachandar ,  Devadatta Bhat

IPC分类号： G11C29/00 ,  G11C29/38 ,  G11C29/44 ,  G11C29/12

CPC分类号： G11C29/38 ,  G11C29/44 ,  G11C2029/1208

摘要： Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

公开(公告)号：US20160293272A1

公开(公告)日：2016-10-06

申请号：US14676501

申请日：2015-04-01

申请人： QUALCOMM Incorporated

发明人： Ashutosh Anand ,  Shankarnarayan Bhat ,  Nikhil Sudhakaran ,  Praveen Raghuraman ,  Nishi Bhushan Singh ,  Anand Bhat ,  Abhinav Kothiala ,  Sanjay Muchini ,  Arun Balachandar ,  Devadatta Bhat

IPC分类号： G11C29/38 ,  G11C29/44 ,  G11C29/36

CPC分类号： G11C29/38 ,  G11C29/44 ,  G11C2029/1208

摘要： Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus.

摘要翻译： 本公开中包含的实施例提供了一种用于存储器内置自检（MBIST）的方法。 该方法从加载测试程序开始，可能来自MBIST控制器。 一旦测试程序加载MBIST测试开始。 在测试期间，内存故障被确定并写入故障指示器寄存器。 对失败指示器寄存器的写入与正在进行的MBIST测试并行。 还提供了一种装置。 该装置包括存储器数据读/写块，存储器寄存器，存储器寻址器和存储器读/写控制器。 该装置通过存储器地址和数据总线与待测存储器进行通信。

公开(公告)号：US20180005663A1

公开(公告)日：2018-01-04

申请号：US15197588

申请日：2016-06-29

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman ,  Nikhil Sudhakaran

IPC分类号： G11B20/18

CPC分类号： G11C29/00 ,  G11C29/12015 ,  G11C29/36 ,  G11C2029/0407 ,  G11C2029/3602

摘要： A method and apparatus for dynamic memory mode testing is provided. The method begins when an electronic device is reset before testing begins. A BIST mode is selected and then input to a BIST apparatus. The BIST mode is then performed and test results recorded. An additional BIST mode is then selected and testing using the additional BIST mode begins immediately. The apparatus includes a clock divider, a BIST controller in communication with the clock divider; a dynamic memory test module in communication with the clock divider, BIST controller and memory; and a low voltage test access port in communication with the BIST controller for receiving test output data from the BIST controller. The dynamic memory test module comprises: at least two AND gates in communication with at least three multiplexers.

公开(公告)号：US20170278583A1

公开(公告)日：2017-09-28

申请号：US15081640

申请日：2016-03-25

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman ,  Vaishnavi Sundaralingam ,  Madhura Hegde ,  Nikhil Sudhakaran

IPC分类号： G11C29/12 ,  G06F3/06 ,  G06F11/07

CPC分类号： G11C29/12 ,  G06F11/073 ,  G06F11/0793 ,  G11C17/16 ,  G11C17/18 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/785 ,  G11C2029/4402

摘要： A method and apparatus for repairing a memory is provided. At least one memory is tested using a production test pattern. After the production test, a passing or failing status is determined for each memory tested. This determination may be made using a built-in repair analysis (BIRA) program. After the analysis the location of each failing memory is determined. A fuse register pattern is then determined for the failing memory, and at least one fuse is blown to repair the failed memory. The repair utilizes at least one of the redundant memories present in the semiconductor device. The apparatus includes a semiconductor device having repairable memories, a fuse programmable read-only memory (FPROM) that contains multiple redundant memories, and a fuse box memory repair apparatus that is in communication with the FRPOM and the multiple repairable memories.

公开(公告)号：US11940490B2

公开(公告)日：2024-03-26

申请号：US17990607

申请日：2022-11-18

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman

IPC分类号： G01R31/317 ,  G01R31/3167 ,  G01R31/3177

CPC分类号： G01R31/31718 ,  G01R31/3167 ,  G01R31/31724 ,  G01R31/3177

摘要： The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

公开(公告)号：US11531061B2

公开(公告)日：2022-12-20

申请号：US16983938

申请日：2020-08-03

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman

IPC分类号： G01R31/317 ,  G01R31/3167 ,  G01R31/3177

摘要： The disclosure provides a method and apparatus of interleaved on-chip testing. The method merges a test setup for analog components with a test setup for digital components and then interleaves the execution of the digital components with the analog components. This provides concurrency via a unified mode of operation. The apparatus includes a system-on-chip test access port (SoC TAP) in communication with a memory test access port (MTAP). A built-in self-test (BIST) controller communicates with the MTAP, a physical layer, and a memory. A multiplexer is in communication with the memory and a phase locked loop (PLL) through an AND gate.

公开(公告)号：US20160077151A1

公开(公告)日：2016-03-17

申请号：US14484643

申请日：2014-09-12

申请人： QUALCOMM Incorporated

发明人： Ashutosh Anand ,  Shankarnarayan Bhat ,  Arun Balachandar ,  Nikhil Sudhakaran ,  Praveen Raghuraman ,  Devadatta Bhat ,  Sanjay Muchini

IPC分类号： G01R31/28

CPC分类号： G01R31/318588 ,  G01R31/31719 ,  G11C7/24 ,  G11C29/12

摘要： A method and apparatus for testing secure blocks is provided. The method begins when instructions for testing a secure memory are loaded using a parallel testing interface. Instructions for testing the non-secure memory may be resident on the device as Built-In-Self-Test (BIST) instructions. In that case, the instructions are then accessed through the standard test access. Testing occurs simultaneously for the secure memory and the non-secure memory using both the parallel interface and the standard test interface. Testing both the secure memory blocks and the non-secure memory blocks using the parallel and standard test interfaces saves time during the test process.

摘要翻译： 提供了一种用于测试安全块的方法和装置。 当使用并行测试接口加载用于测试安全存储器的指令时，该方法开始。 用于测试非安全存储器的指令可以作为内置自检（BIST）指令驻留在设备上。 在这种情况下，然后通过标准测试访问访问指令。 同时使用并行接口和标准测试接口同时进行安全存储器和非安全存储器的测试。 使用并行和标准测试接口测试安全内存块和非安全内存块可以节省测试过程中的时间。