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公开(公告)号：US20240178663A1
公开(公告)日：2024-05-30
申请号：US18070414
申请日：2022-11-28
Applicant: QUALCOMM Incorporated
Inventor： Kshitij YADAV , Vijayakumar DHANASEKARAN , Khaled Mahmoud ABDELFATTAH ALY , Ramkumar SIVAKUMAR , Dongyang TANG , Chienchung YANG
IPC: H02H9/04
CPC classification number: H02H9/046
Abstract: An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal couples through a diode to a voltage node. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to pulse a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling the voltage node to a gate of the pass transistor.
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公开(公告)号：US20210231710A1
公开(公告)日：2021-07-29
申请号：US17154758
申请日：2021-01-21
Applicant: QUALCOMM Incorporated
Inventor： Ramkumar SIVAKUMAR , Jingxue LU , Sherif GALAL , Xinwang ZHANG , Kshitij YADAV
Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
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公开(公告)号：US20210297046A1
公开(公告)日：2021-09-23
申请号：US16827280
申请日：2020-03-23
Applicant: QUALCOMM Incorporated
Inventor： Pradeep SILVA , Ramkumar SIVAKUMAR , Qubo ZHOU , Xinwang ZHANG , Hanil LEE , Dongyang TANG , Vijayakumar DHANASEKARAN
Abstract: A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.
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4.发明申请公开(公告)号：US20160284420A1
公开(公告)日：2016-09-29
申请号：US14700696
申请日：2015-04-30
Applicant: QUALCOMM Incorporated
Inventor： Wenchang HUANG , Ramkumar SIVAKUMAR
CPC classification number: G11C27/026 , H03H19/004 , H03M3/342
Abstract: Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.
Abstract translation: 本公开的某些方面通常涉及开关电容积分器的采样网络和与其相关联的时钟方案，其可以例如在模数转换器（ADC）中使用。 积分器通常包括五组开关，其允许与常规双采样网络相比在积分器的输入级降低开关频率（例如，减半）。 结果，积分器的输入阻抗可以增加（例如，加倍），导致较低的功率消耗和减小的驱动电路的应变。
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公开(公告)号：US20240176574A1
公开(公告)日：2024-05-30
申请号：US18072603
申请日：2022-11-30
Applicant: QUALCOMM Incorporated
Inventor： Dongyang TANG , Ramkumar SIVAKUMAR , Khaled Mahmoud ABDELFATTAH ALY
IPC: G06F3/16 , G06F13/38 , H03K17/687
CPC classification number: G06F3/162 , G06F13/38 , H03K17/6871 , G06F2213/0042
Abstract: An integrated circuit is provided with a terminal that functions to pass a data signal during a high-speed data mode of operation and to pass an audio signal during an audio mode of operation. The integrated circuit includes an audio source that couples to the terminal through an audio pass transistor during the audio mode of operation. To maintain the audio pass transistor off during the high-speed data mode of operation, the integrated circuit includes a first transistor coupled between the terminal and a gate of the audio pass transistor. The first transistor conducts negative charge from the terminal to the gate of the audio pass transistor.
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Patent Agency Ranking
公开(公告)号：US20230148160A1
公开(公告)日：2023-05-11
申请号：US17522729
申请日：2021-11-09
Applicant: QUALCOMM Incorporated
Inventor： Ramkumar SIVAKUMAR , Subbarao Surendra CHAKKIRALA
CPC classification number: H02H9/046 , H02H1/0007
Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.
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公开(公告)号：US20230137935A1
公开(公告)日：2023-05-04
申请号：US18146832
申请日：2022-12-27
Applicant: QUALCOMM Incorporated
Inventor： Ramkumar SIVAKUMAR , Jingxue LU , Sherif GALAL , Xinwang ZHANG , Kshitij YADAV
Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
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公开(公告)号：US20240178662A1
公开(公告)日：2024-05-30
申请号：US18070386
申请日：2022-11-28
Applicant: QUALCOMM Incorporated
Inventor： Kshitij YADAV , Vijayakumar DHANASEKARAN , Khaled Mahmoud ABDELFATTAH ALY , Ramkumar SIVAKUMAR
IPC: H02H9/04
CPC classification number: H02H9/046
Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.
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公开(公告)号：US20240162874A1
公开(公告)日：2024-05-16
申请号：US18055996
申请日：2022-11-16
Applicant: QUALCOMM Incorporated
Inventor： Dongyang TANG , Ramkumar SIVAKUMAR , Khaled Mahmoud ABDELFATTAH ALY , Vijayakumar DHANASEKARAN
CPC classification number: H03G5/165 , G06F3/162 , H03F3/183 , H04R3/00 , H04S1/00 , H03F2200/03 , H04R2420/07 , H04R2420/09
Abstract: A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.
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公开(公告)号：US20240162718A1
公开(公告)日：2024-05-16
申请号：US18055306
申请日：2022-11-14
Applicant: QUALCOMM Incorporated
Inventor： Vijayakumar DHANASEKARAN , Ramkumar SIVAKUMAR , Kshitij YADAV , Khaled Mahmoud ABDELFATTAH ALY
IPC: H02J7/00
CPC classification number: H02J7/00034 , H02J7/00308
Abstract: Circuits and methods for suppression of negative transient voltage may be implemented in systems that combine high-speed data, audio, and charging at a plug. The circuits and methods for suppression of the negative transient voltage may include a first diode and transistor coupled in series between a pin and ground, where the transistor is controlled by an output of a voltage comparator that is also coupled to the first pin. A negative transient voltage event may cause the comparator to activate the transistor to sink a current through the diode.
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