VOLTAGE-TO-CURRENT ARCHITECTURE AND ERROR CORRECTION SCHEMES

    公开(公告)号:US20210231710A1

    公开(公告)日:2021-07-29

    申请号:US17154758

    申请日:2021-01-21

    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR
    4.
    发明申请
    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR 有权
    开关电容器整流器的采样网络和时钟方案

    公开(公告)号:US20160284420A1

    公开(公告)日:2016-09-29

    申请号:US14700696

    申请日:2015-04-30

    CPC classification number: G11C27/026 H03H19/004 H03M3/342

    Abstract: Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

    Abstract translation: 本公开的某些方面通常涉及开关电容积分器的采样网络和与其相关联的时钟方案,其可以例如在模数转换器(ADC)中使用。 积分器通常包括五组开关,其允许与常规双采样网络相比在积分器的输入级降低开关频率(例如,减半)。 结果,积分器的输入阻抗可以增加(例如,加倍),导致较低的功率消耗和减小的驱动电路的应变。

    AREA EFFICIENT LEVEL TRANSLATING TRIGGER CIRCUIT FOR ELECTROSTATIC DISCHARGE EVENTS

    公开(公告)号:US20230148160A1

    公开(公告)日:2023-05-11

    申请号:US17522729

    申请日:2021-11-09

    CPC classification number: H02H9/046 H02H1/0007

    Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

    VOLTAGE-TO-CURRENT ARCHITECTURE AND ERROR CORRECTION SCHEMES

    公开(公告)号:US20230137935A1

    公开(公告)日:2023-05-04

    申请号:US18146832

    申请日:2022-12-27

    Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.

    FULLY DIFFERENTIAL ESD CIRCUIT FOR HIGH-FREQUENCY APPLICATIONS

    公开(公告)号:US20240178662A1

    公开(公告)日:2024-05-30

    申请号:US18070386

    申请日:2022-11-28

    CPC classification number: H02H9/046

    Abstract: A differential ESD circuit is provided for protecting a pair of differential terminals of an integrated circuit from electrostatic shock. A first diode couples between a first terminal in the pair of differential terminals and a first resistor that couples to a voltage node of the integrated circuit. Similarly, a second diode couples between a second terminal in the pair of differential terminals and a second resistor that couples to the voltage node of the integrated circuit. The first and second resistors isolate the first and second terminals from a capacitive loading that would otherwise exist from the first and second diodes.

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