公开(公告)号：US20240178663A1

公开(公告)日：2024-05-30

申请号：US18070414

申请日：2022-11-28

Applicant: QUALCOMM Incorporated

Inventor： Kshitij YADAV ,  Vijayakumar DHANASEKARAN ,  Khaled Mahmoud ABDELFATTAH ALY ,  Ramkumar SIVAKUMAR ,  Dongyang TANG ,  Chienchung YANG

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: An ESD trigger circuit is provided for protecting a pass transistor coupled to an integrated circuit terminal. The integrated circuit terminal couples through a diode to a voltage node. In response to an electrostatic shock at the integrated circuit terminal, the diode conducts charge to the voltage node to pulse a voltage of the voltage node. The ESD trigger circuit responds to the pulse of the voltage by coupling the voltage node to a gate of the pass transistor.

公开(公告)号：US20240162874A1

公开(公告)日：2024-05-16

申请号：US18055996

申请日：2022-11-16

Applicant: QUALCOMM Incorporated

Inventor： Dongyang TANG ,  Ramkumar SIVAKUMAR ,  Khaled Mahmoud ABDELFATTAH ALY ,  Vijayakumar DHANASEKARAN

IPC: H03G5/16 ,  G06F3/16 ,  H03F3/183 ,  H04R3/00 ,  H04S1/00

CPC classification number: H03G5/165 ,  G06F3/162 ,  H03F3/183 ,  H04R3/00 ,  H04S1/00 ,  H03F2200/03 ,  H04R2420/07 ,  H04R2420/09

Abstract: A transmission line includes an equalization circuit. The equalization circuit is a second-order equalization circuit having a first loop at a gain element and a second loop at the gain element. The first loop may include a first compensation capacitor, and the second loop may include a second compensation capacitor and a resistor. The second order equalization circuit may allow for improved performance with respect to gain as well as reduced power usage.

公开(公告)号：US20240176574A1

公开(公告)日：2024-05-30

申请号：US18072603

申请日：2022-11-30

Applicant: QUALCOMM Incorporated

Inventor： Dongyang TANG ,  Ramkumar SIVAKUMAR ,  Khaled Mahmoud ABDELFATTAH ALY

IPC: G06F3/16 ,  G06F13/38 ,  H03K17/687

CPC classification number: G06F3/162 ,  G06F13/38 ,  H03K17/6871 ,  G06F2213/0042

Abstract: An integrated circuit is provided with a terminal that functions to pass a data signal during a high-speed data mode of operation and to pass an audio signal during an audio mode of operation. The integrated circuit includes an audio source that couples to the terminal through an audio pass transistor during the audio mode of operation. To maintain the audio pass transistor off during the high-speed data mode of operation, the integrated circuit includes a first transistor coupled between the terminal and a gate of the audio pass transistor. The first transistor conducts negative charge from the terminal to the gate of the audio pass transistor.

公开(公告)号：US20230238925A1

公开(公告)日：2023-07-27

申请号：US17648958

申请日：2022-01-26

Applicant: QUALCOMM Incorporated

Inventor： Dongyang TANG ,  Xinwang ZHANG ,  ChienChung YANG ,  Earl SCHREYER ,  Sherif GALAL

IPC: H03F3/217

CPC classification number: H03F3/217 ,  H03F2200/03

Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.

公开(公告)号：US20240322685A1

公开(公告)日：2024-09-26

申请号：US18189120

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA ,  Dongyang TANG

IPC: H02M3/158 ,  H04R3/00

CPC classification number: H02M3/158 ,  H04R3/00

Abstract: Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to power supply circuit. The power supply circuit may include at least one voltage supply selectively coupled to an output node of the power supply circuit, and a boost converter having: an inductive element coupled to a power source and a switching node; a first transistor coupled between the switching node and a reference potential node; a second transistor having a drain coupled to the switching node; and a third transistor having a source coupled to a source of the second transistor, a drain of the third transistor being coupled to the output node.

公开(公告)号：US20230058434A1

公开(公告)日：2023-02-23

申请号：US17404862

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： ChienChung YANG ,  Dongyang TANG ,  Sherif GALAL ,  Xinwang ZHANG ,  Subbarao Surendra CHAKKIRALA ,  Pradeep SILVA

IPC: H03F1/32 ,  H03F3/217

Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.

公开(公告)号：US20210297046A1

公开(公告)日：2021-09-23

申请号：US16827280

申请日：2020-03-23

Applicant: QUALCOMM Incorporated

Inventor： Pradeep SILVA ,  Ramkumar SIVAKUMAR ,  Qubo ZHOU ,  Xinwang ZHANG ,  Hanil LEE ,  Dongyang TANG ,  Vijayakumar DHANASEKARAN

IPC: H03F1/02 ,  H03F3/21

Abstract: A power amplifier provides reduction of click and pop in audio applications. The power amplifier includes a first amplifier and an auxiliary amplifier. The auxiliary amplifier is used to ramp the power amplifier output from ground to an offset voltage to reduce the “click and pop” sound. The first amplifier and the auxiliary amplifier having a shared feedback loop. An output of the first amplifier and an output of the auxiliary amplifier may be switchably coupled to the shared feedback loop. A wave generator controls a switch to couple the first amplifier output or the auxiliary amplifier output to the shared feedback loop.

公开(公告)号：US20170063368A1

公开(公告)日：2017-03-02

申请号：US14835222

申请日：2015-08-25

Applicant: QUALCOMM INCORPORATED

Inventor： Dongyang TANG ,  Vijayakumar DHANASEKARAN

IPC: H03K17/687 ,  H03M1/66 ,  H03M1/10

CPC classification number: H03M1/66 ,  G05F3/24 ,  H03F1/301 ,  H03F3/3022 ,  H03F2200/453 ,  H03K17/063 ,  H03M1/0612 ,  H03M1/808

Abstract: Certain aspects of the present disclosure provide methods and apparatus for setting a voltage level for controlling at least one of a first switch or a second switch, such that an on-resistance of the first switch matches an on-resistance of the second switch. One example circuit generally includes a third switch configured to replicate the first switch and a first cascode device connected in cascode with the third switch; a first amplifier configured to drive the first cascode device; a fourth switch configured to replicate the second switch; a second cascode device connected in cascode with the fourth switch; a second amplifier configured to drive the second cascode device; and a third amplifier configured to compare a voltage at a node coupled to the first and second cascode devices with a reference potential and to control the third switch based on the comparison to set the voltage level.

Abstract translation: 本公开的某些方面提供了用于设置用于控制第一开关或第二开关中的至少一个的电压电平的方法和装置，使得第一开关的导通电阻与第二开关的导通电阻相匹配。 一个示例电路通常包括被配置为复制第一开关的第三开关和与第三开关并联连接的第一共源共用器件; 第一放大器，被配置为驱动所述第一共源共用器件; 配置为复制所述第二开关的第四开关; 与第四开关串联连接的第二共源共用器件; 第二放大器，被配置为驱动所述第二共源共用器件; 以及第三放大器，其被配置为将耦合到所述第一和第二共源共栅器件的节点处的电压与参考电位进行比较，并且基于所述比较来控制所述第三开关以设置所述电压电平。