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公开(公告)号：US09864647B2
公开(公告)日：2018-01-09
申请号：US14588798
申请日：2015-01-02
发明人： Serag Gadelrab , Cristian Duroiu , Vinod Chamarty , Pooja Sinha , John Daniel Chaparro , Anil Vootukuru , Vinodh Ramesh Cuppu , Joseph Schweiray Lee , Vinay Mitter , Paul Chow , Ruolong Liu , Johnny Jone Wai Kuan
CPC分类号： G06F11/0781 , G06F1/08 , G06F11/0742 , G06F11/0793 , G06F13/4022
摘要： A method and system for adjusting bandwidth within a portable computing device based on danger signals monitored from one on more elements of the portable computing device are disclosed. A danger level of an unacceptable deadline miss (“UDM”) element of the portable computing device may be determined with a danger level sensor within the UDM element. Next, a quality of service (“QoS”) controller may adjust a magnitude for one or more danger levels received based on the UDM element type that generated the danger level and based on a potential fault condition type associated with the particular danger level. The danger levels received from one UDM element may be mapped to at least one of another UDM element and a non-UDM element. A quality of service policy for each UDM element and non-UDM element may be mapped in accordance with the danger levels.
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2.发明授权公开(公告)号：US10019380B2
公开(公告)日：2018-07-10
申请号：US14866228
申请日：2015-09-25
发明人： Serag Monier GadelRab , Jason Edward Podaima , Ruolong Liu , Alexander Miretsky , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Simon Peter William Booth , Meghal Varia , Thomas David Dryburgh
IPC分类号： G06F12/00 , G06F12/1072 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1072 , G06F2212/1008 , G06F2212/1016
摘要： Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
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3.发明申请公开(公告)号：US20170091116A1
公开(公告)日：2017-03-30
申请号：US14866228
申请日：2015-09-25
发明人： Serag Monier GadelRab , Jason Edward Podaima , Ruolong Liu , Alexander Miretsky , Paul Christopher John Wiercienski , Kyle John Ernewein , Carlos Javier Moreira , Simon Peter William Booth , Meghal Varia , Thomas David Dryburgh
IPC分类号： G06F12/10
CPC分类号： G06F12/1072 , G06F2212/1008 , G06F2212/1016
摘要： Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
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