公开(公告)号：US09824015B2

公开(公告)日：2017-11-21

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

CPC classification number: G06F12/0848 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/50 ,  G06F2212/601 ,  G06F2212/68 ,  G06F2212/70 ,  Y02D10/13

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

公开(公告)号：US20160350222A1

公开(公告)日：2016-12-01

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F12/1036 ,  G06F12/109 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/50 ,  G06F2212/601 ,  G06F2212/68 ,  G06F2212/70 ,  Y02D10/13

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, in one aspect, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Abstract translation: 提供存储器管理单元（MMU）分区转换高速缓存以及相关设备，方法和计算机可读介质。 在这方面，在一方面，提供了包括MMU的装置。 MMU包括提供定义地址转换映射的多个转换高速缓存条目的翻译高速缓存。 所述MMU还包括分区描述符表，其提供多个分区描述符，所述分区描述符定义相应的多个分区，每个分区包括所述多个转换高速缓存条目中的一个或多个转换高速缓存条目。 MMU还包括被配置为从请求者接收存储器访问请求的分区转换电路。 分区翻译电路还被配置为确定存储器访问请求的翻译高速缓存分区标识符（TCPID），基于TCPID识别多个分区中的一个或多个分区，并且在翻译高速缓存条目上执行存储器访问请求 一个或多个分区。

公开(公告)号：US09747213B2

公开(公告)日：2017-08-29

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

公开(公告)号：US10007619B2

公开(公告)日：2018-06-26

申请号：US14859351

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Carlos Javier Moreira ,  Alexander Miretsky ,  Meghal Varia ,  Kyle John Ernewein ,  Manokanthan Somasundaram ,  Muhammad Umar Choudry ,  Serag Monier Gadelrab

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/1045 ,  G06F12/0891 ,  G06F12/0844 ,  G06F12/1036 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0806 ,  G06F12/0842 ,  G06F12/0844 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1036 ,  G06F2212/1024 ,  G06F2212/50 ,  G06F2212/655 ,  G06F2212/682 ,  G06F2212/683 ,  G06F2212/684

Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

公开(公告)号：US10019380B2

公开(公告)日：2018-07-10

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/00 ,  G06F12/1072 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US20170091116A1

公开(公告)日：2017-03-30

申请号：US14866228

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Serag Monier GadelRab ,  Jason Edward Podaima ,  Ruolong Liu ,  Alexander Miretsky ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Simon Peter William Booth ,  Meghal Varia ,  Thomas David Dryburgh

IPC: G06F12/10

CPC classification number: G06F12/1072 ,  G06F2212/1008 ,  G06F2212/1016

Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.

公开(公告)号：US09836410B2

公开(公告)日：2017-12-05

申请号：US14865965

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Alexander Miretsky

IPC: G06F12/00 ,  G06F12/1027 ,  G06F12/1036 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0864 ,  G06F12/0895

CPC classification number: G06F12/1027 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/1036 ,  G06F2212/1021 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/50 ,  G06F2212/652 ,  G06F2212/654 ,  G06F2212/683

Abstract: A comparand that includes a virtual address is received. Upon determining a match of the comparand to a burst entry tag, a candidate matching translation data unit is selected. The selecting is from a plurality of translation data units associated with the burst entry tag, and is based at least in part on at least one bit of the virtual address. Content of the candidate matching translation data unit is compared to at least a portion of the comparand. Upon a match, a hit is generated.

公开(公告)号：US09785559B2

公开(公告)日：2017-10-10

申请号：US14725882

申请日：2015-05-29

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Bohuslav Rychlik ,  Carlos Javier Moreira ,  Serag Monier GadelRab ,  Paul Christopher John Wiercienski ,  Alexander Miretsky ,  Kyle John Ernewein

IPC: G06F12/12 ,  G06F12/0846 ,  G06F12/1036 ,  G06F12/109

Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.