公开(公告)号：US20180225066A1

公开(公告)日：2018-08-09

申请号：US15944041

申请日：2018-04-03

申请人： QUALCOMM Incorporated

发明人： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC分类号： G06F3/06 ,  G06F1/32 ,  G06F12/08

CPC分类号： G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US09965220B2

公开(公告)日：2018-05-08

申请号：US15016806

申请日：2016-02-05

申请人： QUALCOMM Incorporated

发明人： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Haw-Jing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC分类号： G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US09734070B2

公开(公告)日：2017-08-15

申请号：US14921468

申请日：2015-10-23

申请人： QUALCOMM INCORPORATED

发明人： Alain Artieri ,  Subbarao Palacharla ,  Laurent Moll ,  Raghu Sankuratri ,  Kedar Bhole ,  Vinod Chamarty

IPC分类号： G06F12/08 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/0864 ,  G06F12/123

CPC分类号： G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

摘要： A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20160019157A1

公开(公告)日：2016-01-21

申请号：US14333981

申请日：2014-07-17

申请人： QUALCOMM Incorporated

发明人： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Pankaj Chaurasia ,  Raghu Sankuratri

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/12

CPC分类号： G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/10 ,  G06F12/12 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6046 ,  Y02D10/13

摘要： Aspects include computing devices, systems, and methods for partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests specifying component cache identifiers, and match the component cache identifiers with records correlating traits of the component cache identifiers with in a component cache configuration table. The component cache traits may include a set shift trait, set offset trait, and target ways, which may define the locations of the component caches in the system cache. The system cache memory controller may also receive a physical address for the system cache in the system cache access request, determine an indexing mode for the component cache, and translate the physical address for the component cache.

摘要翻译： 方面包括计算设备，系统和用于通过集合和方式将系统高速缓存分组到组件高速缓存中的方法。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收指定组件高速缓存标识符的系统高速缓存访​​问请求，并且将组件高速缓存标识符与组件高速缓存标识符的特征与组件高速缓存配置表相关联的记录进行匹配。 组件缓存特征可以包括设置的移动特征，设置偏移特征和目标方式，其可以定义系统高速缓存中的组件高速缓存的位置。 系统高速缓冲存储器控制器还可以在系统高速缓存访​​问请求中接收系统高速缓存的物理地址，确定组件高速缓存的索引模式，并转换组件高速缓存的物理地址。

公开(公告)号：US10761774B2

公开(公告)日：2020-09-01

申请号：US15944041

申请日：2018-04-03

申请人： QUALCOMM Incorporated

发明人： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Michael Hawjing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC分类号： G06F1/32 ,  G06F12/08 ,  G06F3/06 ,  G06F1/3234

摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

公开(公告)号：US20170116118A1

公开(公告)日：2017-04-27

申请号：US14921468

申请日：2015-10-23

申请人： QUALCOMM INCORPORATED

发明人： ALAIN ARTIERI ,  SUBBARAO PALACHARLA ,  LAURENT MOLL ,  RAGHU SANKURATRI ,  Kedar Bhloe ,  Vinod Chamarty

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0842 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/123 ,  G06F12/127 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/601 ,  G06F2212/62

摘要： A cache controller adaptively partitions a shared cache. The adaptive partitioning cache controller includes tag comparison and staling logic and selection logic that are responsive to client access requests and various parameters. A component cache is assigned a target occupancy which is compared to a current occupancy. A conditional identification of stale cache lines is used to manage data stored in the shared cache. When a conflict or cache miss is identified, selection logic identifies candidates for replacement preferably among cache lines identified as stale. Each cache line is assigned to a bucket with a fixed number of buckets per component cache. Allocated cache lines are assigned to a bucket as a function of the target occupancy. After a select number of buckets are filled, subsequent allocations result in the oldest cache lines being marked stale. Cache lines are deemed stale when their respective component cache active indicator is de-asserted.

公开(公告)号：US20160019158A1

公开(公告)日：2016-01-21

申请号：US14334010

申请日：2014-07-17

申请人： QUALCOMM Incorporated

发明人： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edward Turner ,  Jeong-Ho Woo

IPC分类号： G06F12/08

CPC分类号： G06F12/0893 ,  G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/50 ,  G06F12/084 ,  G06F12/0864 ,  G06F12/0888 ,  G06F12/0895 ,  G06F17/30902 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  Y02D10/13

摘要： Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

摘要翻译： 方面包括计算设备，系统和方法，用于通过集合和方式动态地将系统高速缓存分区到组件高速缓存中。 系统高速缓冲存储器控制器可以管理组件高速缓存并管理对组件高速缓存的访问。 系统高速缓冲存储器控制器可以接收系统高速缓存访​​问请求，并且在系统高速缓存中保留对应于与请求的组件高速缓存标识符相关联的组件高速缓存的位 在系统缓存中预留位置可以激活系统高速缓存中的位置以供请求客户端使用，并且还可以防止其他客户端使用系统高速缓存中的保留位置。 释放系统缓存中的位置可以停用系统缓存中的位置，并允许其他客户端使用它们。 保留系统缓存中的位置的客户端可以改变其在其组件高速缓存中保留的位置的数量。

公开(公告)号：US20240320125A1

公开(公告)日：2024-09-26

申请号：US18528225

申请日：2023-12-04

申请人： QUALCOMM Incorporated

发明人： Gaurav Sanjeev Kirtane ,  Vinod Chamarty

IPC分类号： G06F11/34

CPC分类号： G06F11/348 ,  G06F11/3495

摘要： Tracing circuits are disposed within each node circuit in a mesh network to debug problems found during development. The tracing circuit disclosed includes a trace read interface for accessing trace packets stored in a trace buffer at entries that are mapped to system memory addresses. Processing circuits coupled to the trace read interface may access the stored trace packets using memory instructions. The trace packets include trace information generated from packets that are detected on selected ports of a node circuit in a node of the mesh network. A filter circuit compares the transaction units to a trace criteria and stores the trace information of the matching packets in the form of trace packets in the memory-mapped entries of the trace buffer. The trace packets can include the transaction units of a packet or just packet header information for more efficient use of the trace buffer.

公开(公告)号：US20240202087A1

公开(公告)日：2024-06-20

申请号：US18498583

申请日：2023-10-31

申请人： QUALCOMM Incorporated

发明人： Sreeram Jayadev ,  Vinod Chamarty

IPC分类号： G06F11/22

CPC分类号： G06F11/2221

摘要： Routing raw debug data using trace infrastructure in processor-based devices is disclosed. In some aspects, a processor-based device comprises a trace interconnect bus, a subsystem circuit comprising a debug transmit circuit, and an input/output (I/O) endpoint circuit. The debug transmit circuit is configured to receive raw debug data from the subsystem circuit, and generate a debug trace packet comprising the raw debug data in lieu of formatted trace data. The debug transmit circuit is also configured to transmit the debug trace packet comprising the raw debug data to the I/O endpoint circuit via the trace interconnect bus during a period of trace interconnect bus inactivity. In this manner, an existing trace infrastructure can be employed to transmit raw debug data without incurring expense in terms of overhead and monetary cost due to the need for industry-standard, infrastructure-compliant tools to decode conventionally packetized trace data for analysis.

公开(公告)号：US10089238B2

公开(公告)日：2018-10-02

申请号：US14334010

申请日：2014-07-17

申请人： QUALCOMM Incorporated

发明人： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edmund Turner ,  Jeong-Ho Woo

IPC分类号： G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/50 ,  G06F12/0888 ,  G06F12/0864 ,  G06F1/32 ,  G06F17/30

摘要： Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.