公开(公告)号：US10454509B2

公开(公告)日：2019-10-22

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan ,  Ashok Swaminathan ,  Shahin Mehdizad Taleie ,  Yen-Wei Chang ,  Vinod Panikkath ,  Sameer Vasantlal Vora ,  Ayush Mittal ,  Tonmoy Biswas ,  Sy-Chyuan Hwu ,  Zhilong Tang ,  Ibrahim Chamas ,  Ping Wing Lai ,  Behnam Sedighi ,  Dongwon Seo ,  Nitz Saputra

IPC: H04B1/04 ,  H04L27/20 ,  H04B1/00

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20170085986A1

公开(公告)日：2017-03-23

申请号：US14858306

申请日：2015-09-18

Applicant: Qualcomm Incorporated

Inventor： Zhilong Tang ,  Jingxue Lu

IPC: H04R3/00 ,  H04R29/00

CPC classification number: H04R3/007 ,  H04R29/001 ,  H04R2203/00 ,  H04R2430/01

Abstract: A method of protecting a speaker from thermal damage includes determining a first load current through a first resistor that is coupled to the speaker. The method also includes converting the first load current to a digital value using a second load current through a second resistor as a reference input. The second resistor is part of a circuit that reduces an effect of a temperature coefficient of resistance of the first resistor. The method also includes comparing the digital value of the first load current to a threshold value. The method further includes, responsive to the first load current being larger than the threshold value, generating an instruction to take an action to protect the speaker.

公开(公告)号：US09369272B2

公开(公告)日：2016-06-14

申请号：US14227235

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhilong Tang ,  Khosro Mohammad Rabii ,  Matthew David Sienko

IPC: G06F1/12 ,  G06F13/42 ,  H04L7/04 ,  G06F11/10 ,  H04J3/06

CPC classification number: H04L7/048 ,  G06F11/1004 ,  G06F13/4286 ,  G06F13/4295 ,  H04J3/0644 ,  H04J3/0652

Abstract: One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

Abstract translation: 一个特征涉及将音频处理子系统（即本地节点）与音频编码器 - 解码器（CODEC）子系统（即，远程节点）相互连接的串行时分多路复用总线的同步。控制信号沿双向传输 总线的传输线从音频处理子系统到音频CODEC子系统。 当发送控制信号时，音频处理子系统跟踪内部状态机相位计数。 随着信号被接收，音频CODEC子系统还跟踪内部状态机相位计数。 音频处理子系统的控制信号的传输基于相位计数周期性地暂停或暂停一段固定的时间间隔，以允许音频CODEC子系统将同步指示符信号发送回音频处理子系统使用的音频处理子系统 验证同步。 这可以例如每一百二十个相位计数执行一次。

公开(公告)号：US11539371B1

公开(公告)日：2022-12-27

申请号：US17449056

申请日：2021-09-27

Applicant: QUALCOMM Incorporated

Inventor： Zhilong Tang ,  Dongwon Seo

IPC: H03M1/10

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current sources, a plurality of calibration DACs, each coupled to a respective one of the plurality of current sources, a reference current source, and a current mirror having a first branch selectively coupled to the plurality of current sources, wherein a second branch of the current mirror is coupled to the reference current source. The DAC system also includes a first error DAC selectively coupled to the first branch and the second branch of the current mirror, and a second error DAC selectively coupled to the first branch and the second branch of the current mirror.

公开(公告)号：US09749739B2

公开(公告)日：2017-08-29

申请号：US14858306

申请日：2015-09-18

Applicant: Qualcomm Incorporated

Inventor： Zhilong Tang ,  Jingxue Lu

IPC: H03G11/00 ,  H04R3/00 ,  H04R29/00

CPC classification number: H04R3/007 ,  H04R29/001 ,  H04R2203/00 ,  H04R2430/01

Abstract: A method of protecting a speaker from thermal damage includes determining a first load current through a first resistor that is coupled to the speaker. The method also includes converting the first load current to a digital value using a second load current through a second resistor as a reference input. The second resistor is part of a circuit that reduces an effect of a temperature coefficient of resistance of the first resistor. The method also includes comparing the digital value of the first load current to a threshold value. The method further includes, responsive to the first load current being larger than the threshold value, generating an instruction to take an action to protect the speaker.

公开(公告)号：US09501261B2

公开(公告)日：2016-11-22

申请号：US14271402

申请日：2014-05-06

Applicant: QUALCOMM Incorporated

Inventor： Zhilong Tang

IPC: G06F7/00 ,  G06F7/485 ,  H03M1/08 ,  H03M1/06 ,  H03M1/74

CPC classification number: G06F7/485 ,  H03M1/0639 ,  H03M1/0863 ,  H03M1/74

Abstract: A binary array system and method for operating an electrical system are disclosed. The binary array system includes a binary counter configured to output a number of bit values through a number of bit outputs. Each of the bit values are output through a corresponding one of the bit outputs. The system includes a number of binary array elements. Each of the binary array elements is coupled to a corresponding one of the bit outputs and is configured to provide a unit value based on one of the bit values output through the corresponding one of the bit outputs. The binary array system also includes a controller coupled to the binary counter that is configured to set the bit values of the binary counter.

Abstract translation: 公开了用于操作电气系统的二进制阵列系统和方法。 二进制数组系统包括二进制计数器，配置为通过多个位输出输出多个位值。 每个位值通过相应的一个位输出输出。 该系统包括多个二进制数组元素。 每个二进制数组元件被耦合到对应的一个比特输出，并且被配置为基于通过相应的一个比特输出输出的比特值之一来提供单位值。 二进制数组系统还包括耦合到二进制计数器的控制器，其被配置为设置二进制计数器的位值。

公开(公告)号：US20150280904A1

公开(公告)日：2015-10-01

申请号：US14227235

申请日：2014-03-27

Applicant: QUALCOMM Incorporated

Inventor： Zhilong Tang ,  Khosro Mohammad Rabii ,  Matthew David Sienko

IPC: H04L7/04 ,  G06F11/10

CPC classification number: H04L7/048 ,  G06F11/1004 ,  G06F13/4286 ,  G06F13/4295 ,  H04J3/0644 ,  H04J3/0652

Abstract: One feature pertains to the synchronization of a serial time-division-multiplexed bus interconnecting an audio processing subsystem (i.e. a local node) with an audio coder-decoder (CODEC) subsystem (i.e. a remote node.) Control signals are transmitted along a bidirectional transmission line of the bus from the audio processing subsystem to the audio CODEC subsystem. The audio processing subsystem tracks an internal state machine phase count as the control signals are transmitted. The audio CODEC subsystem also tracks an internal state machine phase count as the signals are received. Transmission of control signals by the audio processing subsystem is periodically paused or suspended for a fixed interval of time based on the phase count to allow the audio CODEC subsystem to send a synchronization indicator signal back to the audio processing subsystem, which the audio processing subsystem uses to verify synchronization. This may be performed, for example, once every one hundred-twenty phase counts.

Abstract translation: 一个特征涉及将音频处理子系统（即，本地节点）与音频编码器 - 解码器（CODEC）子系统（即，远程节点）相互连接的串行时分多路复用总线的同步。控制信号沿双向传输 总线的传输线从音频处理子系统到音频CODEC子系统。 当发送控制信号时，音频处理子系统跟踪内部状态机相位计数。 随着信号被接收，音频CODEC子系统还跟踪内部状态机相位计数。 音频处理子系统的控制信号的传输基于相位计数周期性地暂停或暂停一段固定的时间间隔，以允许音频CODEC子系统将同步指示符信号发送回音频处理子系统使用的音频处理子系统 验证同步。 这可以例如每一百二十个相位计数执行一次。