公开(公告)号：US12100474B2

公开(公告)日：2024-09-24

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong Xu ,  Satish Krishnamoorthy ,  Boris Dimitrov Andreev ,  Patrick Isakanian ,  Farrukh Aquil ,  Vikas Mahendiyan ,  Ravindra Arvind Khedkar

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US11916558B1

公开(公告)日：2024-02-27

申请号：US18080728

申请日：2022-12-13

Applicant: QUALCOMM Incorporated

Inventor： Yong Xu ,  Boris Dimitrov Andreev ,  Vikas Mahendiyan ,  Yuxin Li ,  Anand Meruva ,  Jeffrey Mark Hinrichs

IPC: H03L7/00 ,  G06F1/12 ,  H03K19/20 ,  H03L7/081

CPC classification number: H03L7/0812 ,  G06F1/12 ,  H03K19/20

Abstract: A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.