公开(公告)号：US09305632B2

公开(公告)日：2016-04-05

申请号：US13901511

申请日：2013-05-23

申请人： QUALCOMM Incorporated

发明人： Zeeshan Shafaq Syed ,  Nan Chen ,  Yong Xu ,  Michael Thomas Fertsch ,  Boris Dimitrov Andreev ,  Zhiqin Chen ,  Chang Ki Kwon

IPC分类号： G06F1/32 ,  G11C11/4074

CPC分类号： G11C11/4074 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

摘要翻译： 提供了一种方法和装置。 该装置是控制多个模块的功率模式的硬件模块。 该装置接收到期望的操作频率的指示。 基于接收到的指示，设备确定从与第一组模块相关联的第一功率模式切换到对应于期望操作频率并与第二组模块相关联的第二功率模式。 该装置使得与第一功率模式不相关的第二组模块中的模块在启用与第一功率模式不相关的第二组模块中的模块之后的一段时间期满后停止通过多个模块的业务 通过第二组模块路由流量，并禁用与第二功率模式无关的第一组模块中的模块。

公开(公告)号：US11916558B1

公开(公告)日：2024-02-27

申请号：US18080728

申请日：2022-12-13

申请人： QUALCOMM Incorporated

发明人： Yong Xu ,  Boris Dimitrov Andreev ,  Vikas Mahendiyan ,  Yuxin Li ,  Anand Meruva ,  Jeffrey Mark Hinrichs

IPC分类号： H03L7/00 ,  G06F1/12 ,  H03K19/20 ,  H03L7/081

CPC分类号： H03L7/0812 ,  G06F1/12 ,  H03K19/20

摘要： A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

公开(公告)号：US12100474B2

公开(公告)日：2024-09-24

申请号：US17954852

申请日：2022-09-28

申请人： QUALCOMM Incorporated

发明人： Yong Xu ,  Satish Krishnamoorthy ,  Boris Dimitrov Andreev ,  Patrick Isakanian ,  Farrukh Aquil ,  Vikas Mahendiyan ,  Ravindra Arvind Khedkar

IPC分类号： G11C7/10 ,  G11C7/14 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C7/1066 ,  G11C7/14

摘要： A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US11971741B2

公开(公告)日：2024-04-30

申请号：US17396046

申请日：2021-08-06

申请人： QUALCOMM Incorporated

发明人： Mukund Narasimhan ,  Murali Krishna Ade ,  Arun David Arul Diraviyam ,  Mayank Gupta ,  Boris Dimitrov Andreev

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F9/30 ,  G06F9/54

CPC分类号： G06F1/10 ,  G06F1/12 ,  G06F9/30134 ,  G06F9/544

摘要： Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.