利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.015 秒)

    Systems and Methods for Setting Logic to a Desired Leakage State
    3.
    发明申请
    Systems and Methods for Setting Logic to a Desired Leakage State 有权
    将逻辑设置为期望泄漏状态的系统和方法

    公开(公告)号：US20160072480A1

    公开(公告)日：2016-03-10

    申请号：US14482403

    申请日：2014-09-10

    申请人： QUALCOMM Incorporated

    发明人： Ryan Michael Coutts ,  Wai Kit Siu ,  Paul Ivan Penzes

    IPC分类号： H03K3/012 ,  G05B19/045 ,  H03K17/22 ,  H03K3/037

    CPC分类号： H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

    摘要： Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

    摘要翻译： 提供了减少泄漏的电路和方法。 在一个示例中，系统包括将特定逻辑电路复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路包括组合逻辑以及将状态输出到组合逻辑的触发器。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。

    Systems and methods for setting logic to a desired leakage state
    5.
    发明授权
    Systems and methods for setting logic to a desired leakage state 有权
    将逻辑设置为所需泄漏状态的系统和方法

    公开(公告)号：US09496851B2

    公开(公告)日：2016-11-15

    申请号：US14482403

    申请日：2014-09-10

    申请人： QUALCOMM Incorporated

    发明人： Ryan Michael Coutts ,  Wai Kit Siu ,  Paul Ivan Penzes

    IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K17/22 ,  H03K19/00 ,  G05B19/045

    CPC分类号： H03K3/012 ,  G05B19/045 ,  H03K3/0372 ,  H03K17/223 ,  H03K19/0008

    摘要： Circuits and methods for reducing leakage are provided. In one example, a system includes circuitry to reset a particular logic circuit to a state of reduced leakage. The state of reduced leakage would be known beforehand for the logic circuit. In this example, the logic circuit includes the combinational logic as well as flip flops that output a state to the combinational logic. Some of the flip flops are “SET” flip flops (assuming a 1 output value when a reset input is asserted) and some of the flip flops are “RESET” flip flops (assuming a 0 value when a reset input is asserted). The flip flops are chosen as inputs to the combinational logic so that the particular combination of zeros and ones output to the combinational logic puts the logic circuit in a state that is correlated with a desired level of leakage.

    摘要翻译： 提供了减少泄漏的电路和方法。 在一个示例中，系统包括将特定逻辑电路复位到减少泄漏的状态的电路。 对于逻辑电路，预先知道减少泄漏的状态。 在该示例中，逻辑电路包括组合逻辑以及将状态输出到组合逻辑的触发器。 一些触发器是“SET”触发器（当复位输入被置位时，假定为1个输出值），并且一些触发器是“RESET”触发器（假设复位输入被置位时为0）。 触发器被选择为组合逻辑的输入，使得零和一个输出到组合逻辑的特定组合将逻辑电路置于与期望的泄漏水平相关联的状态。

    CLOCK SWALLOWING DEVICE FOR REDUCING VOLTAGE NOISE
    6.
    发明申请
    CLOCK SWALLOWING DEVICE FOR REDUCING VOLTAGE NOISE 有权
    用于降低电压噪声的闭锁时钟设备

    公开(公告)号：US20150355671A1

    公开(公告)日：2015-12-10

    申请号：US14300084

    申请日：2014-06-09

    申请人： QUALCOMM Incorporated

    发明人： Ryan Michael Coutts ,  Dipti Ranjan Pal

    IPC分类号： G06F1/08

    CPC分类号： G06F1/08 ,  G06F1/206 ,  G06F1/324 ,  H03K21/026 ,  H03K23/662 ,  H03L1/022 ,  Y02D10/126 ,  Y02D10/16

    摘要： Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.

    摘要翻译： 这里描述了通过选择性地吞咽时钟信号中的脉冲来控制时钟信号的频率的系统和方法。 在一个实施例中，一种用于调整时钟信号的频率的方法包括：根据重复的时钟吞咽模式接收时钟信号和吞咽时钟信号中的脉冲，其中，所述模式由数字序列定义。

    Voltage dependent die RC modeling for system level power distribution networks
    9.
    发明授权
    Voltage dependent die RC modeling for system level power distribution networks 有权
    用于系统级配电网络的电压依赖模具RC建模

    公开(公告)号：US09429610B2

    公开(公告)日：2016-08-30

    申请号：US14157451

    申请日：2014-01-16

    申请人： QUALCOMM Incorporated

    发明人： Ryan Michael Coutts

    IPC分类号： G01R27/26 ,  G06F9/455 ,  G06F17/50

    CPC分类号： G01R27/2605 ,  G06F17/5036 ,  G06F2217/78 ,  Y02E60/76 ,  Y04S40/22

    摘要： Techniques for determining the voltage-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining voltage-dependent capacitance of a circuit comprises measuring a parameter of the circuit at each one of a plurality of voltages, and, for each voltage, determining a capacitance of the circuit at the voltage by fitting a resistor-capacitor (RC) model of the circuit to the measured parameter of the circuit at the voltage.

    摘要翻译： 本文描述了用于确定电路的电压相关电容的技术。 在一个实施例中，一种用于确定电路的电压相关电容的方法包括在多个电压中的每一个处测量电路的参数，并且对于每个电压，通过拟合电阻器来确定电路的电容的电容 电容（RC）模型的电路到测量电路的电压参数。