公开(公告)号：US07923683B2

公开(公告)日：2011-04-12

申请号：US12258965

申请日：2008-10-27

申请人： Qi Hua Zhang ,  Chorng Shyr Niou ,  Pan Liu ,  Ming Li

发明人： Qi Hua Zhang ,  Chorng Shyr Niou ,  Pan Liu ,  Ming Li

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： G01N1/286 ,  G01N2001/2873 ,  G01N2033/0095 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g., dynamic random access memory devices, commonly called DRAMS. The method also provides an integrated chip including a thickness, a width, and a length. In a specific embodiment, the integrated chip has at least one elongated structure through a portion of the thickness, while being normal to the width and the length. In a specific embodiment, the elongated structure has a structure width and a structure length that extends through a vertical portion of the thickness. The method includes removing a slice of the integrated chip from a portion of the thickness in a directional manner normal to the structure length. In a specific embodiment, the slice is provided through an entirety of the one elongated structure along the structure length to cause a portion of a thickness of the slice providing the elongated structure to be of a substantially uniform sample thickness. The method also includes capturing one or more images through a portion of the slice using a transmission electron microscope.

摘要翻译： 用于分析用于制造集成电路的样本的方法，例如通常称为DRAMS的动态随机存取存储器件。 该方法还提供了包括厚度，宽度和长度的集成芯片。 在具体实施例中，集成芯片具有穿过厚度的一部分的至少一个细长结构，同时垂直于宽度和长度。 在具体实施例中，细长结构具有延伸穿过厚度的垂直部分的结构宽度和结构长度。 该方法包括以垂直于结构长度的定向方式从厚度的一部分去除集成芯片的切片。 在一个具体的实施例中，切片沿着结构长度通过整个一个细长结构提供，以使切片的厚度的一部分提供细长结构，使其具有基本均匀的样本厚度。 该方法还包括使用透射电子显微镜捕获通过切片的一部分的一个或多个图像。

公开(公告)号：US20100006754A1

公开(公告)日：2010-01-14

申请号：US12258965

申请日：2008-10-27

申请人： Qi Hua Zhang ,  Chorng Shyr Niou ,  Pan Liu ,  Ming Li

发明人： Qi Hua Zhang ,  Chorng Shyr Niou ,  Pan Liu ,  Ming Li

IPC分类号： G01N23/00

CPC分类号： G01N1/286 ,  G01N2001/2873 ,  G01N2033/0095 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g., dynamic random access memory device, commonly called, DRAMS. The method also provides an integrated chip including a thickness, a width, and a length. In a specific embodiment, the integrated chip has at least one elongated structure through a portion of the thickness, while being normal to the width and the length. In a specific embodiment, the elongated structure has a structure width and a structure length that extends through a vertical portion of the thickness. The method includes removing a slice of the integrated circuit chip from a portion of the thickness in a directional manner normal to the structure length. In a specific embodiment, the slice is provided through an entirety of the one elongated structure along the structure length to cause a portion of a thickness of the slice providing the elongated structure to be of a substantially uniform sample thickness. The method also includes capturing one or more images through a portion of the slice using a transmission electron

摘要翻译： 用于分析用于制造集成电路的样本的方法，例如通常称为DRAMS的动态随机存取存储器件。 该方法还提供了包括厚度，宽度和长度的集成芯片。 在具体实施例中，集成芯片具有穿过厚度的一部分的至少一个细长结构，同时垂直于宽度和长度。 在具体实施例中，细长结构具有延伸穿过厚度的垂直部分的结构宽度和结构长度。 该方法包括以垂直于结构长度的定向方式从该厚度的一部分去除集成电路芯片的切片。 在一个具体的实施例中，切片沿着结构长度通过整个一个细长结构提供，以使切片的厚度的一部分提供细长结构，使其具有基本均匀的样本厚度。 该方法还包括使用透射电子通过片的一部分捕获一个或多个图像

公开(公告)号：US07504269B2

公开(公告)日：2009-03-17

申请号：US11378400

申请日：2006-03-16

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： G01R31/26

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

公开(公告)号：US07927893B2

公开(公告)日：2011-04-19

申请号：US12364977

申请日：2009-02-03

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： H01L21/66

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

公开(公告)号：US20090305440A1

公开(公告)日：2009-12-10

申请号：US12364977

申请日：2009-02-03

申请人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

发明人： Qi Hau Zhang ,  Ming Li ,  Chorng Shyr Niou ,  Scott Liao

IPC分类号： H01L21/66 ,  C23C14/34

CPC分类号： G01N23/2276 ,  H01L22/12

摘要： A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

摘要翻译： 用于分析用于制造集成电路的样品的方法，例如， MOS晶体管，专用集成电路，存储器件，微处理器，片上系统。 该方法包括提供集成电路芯片，其具有至少一个感兴趣区域的表面区域，例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层，而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。