Method for treatment of samples for transmission electron microscopes
    1.
    发明授权
    Method for treatment of samples for transmission electron microscopes 有权
    透射电子显微镜样品处理方法

    公开(公告)号:US07923683B2

    公开(公告)日:2011-04-12

    申请号:US12258965

    申请日:2008-10-27

    IPC分类号: G06F17/50 G06K9/00

    摘要: A method for analyzing a sample for the manufacture of integrated circuits, e.g., dynamic random access memory devices, commonly called DRAMS. The method also provides an integrated chip including a thickness, a width, and a length. In a specific embodiment, the integrated chip has at least one elongated structure through a portion of the thickness, while being normal to the width and the length. In a specific embodiment, the elongated structure has a structure width and a structure length that extends through a vertical portion of the thickness. The method includes removing a slice of the integrated chip from a portion of the thickness in a directional manner normal to the structure length. In a specific embodiment, the slice is provided through an entirety of the one elongated structure along the structure length to cause a portion of a thickness of the slice providing the elongated structure to be of a substantially uniform sample thickness. The method also includes capturing one or more images through a portion of the slice using a transmission electron microscope.

    摘要翻译: 用于分析用于制造集成电路的样本的方法,例如通常称为DRAMS的动态随机存取存储器件。 该方法还提供了包括厚度,宽度和长度的集成芯片。 在具体实施例中,集成芯片具有穿过厚度的一部分的至少一个细长结构,同时垂直于宽度和长度。 在具体实施例中,细长结构具有延伸穿过厚度的垂直部分的结构宽度和结构长度。 该方法包括以垂直于结构长度的定向方式从厚度的一部分去除集成芯片的切片。 在一个具体的实施例中,切片沿着结构长度通过整个一个细长结构提供,以使切片的厚度的一部分提供细长结构,使其具有基本均匀的样本厚度。 该方法还包括使用透射电子显微镜捕获通过切片的一部分的一个或多个图像。

    METHOD FOR TREATMENT OF SAMPLES FOR TRANSMISSION ELECTRONIC MICROSCOPES
    2.
    发明申请
    METHOD FOR TREATMENT OF SAMPLES FOR TRANSMISSION ELECTRONIC MICROSCOPES 有权
    用于处理传输电子显微镜样品的方法

    公开(公告)号:US20100006754A1

    公开(公告)日:2010-01-14

    申请号:US12258965

    申请日:2008-10-27

    IPC分类号: G01N23/00

    摘要: A method for analyzing a sample for the manufacture of integrated circuits, e.g., dynamic random access memory device, commonly called, DRAMS. The method also provides an integrated chip including a thickness, a width, and a length. In a specific embodiment, the integrated chip has at least one elongated structure through a portion of the thickness, while being normal to the width and the length. In a specific embodiment, the elongated structure has a structure width and a structure length that extends through a vertical portion of the thickness. The method includes removing a slice of the integrated circuit chip from a portion of the thickness in a directional manner normal to the structure length. In a specific embodiment, the slice is provided through an entirety of the one elongated structure along the structure length to cause a portion of a thickness of the slice providing the elongated structure to be of a substantially uniform sample thickness. The method also includes capturing one or more images through a portion of the slice using a transmission electron

    摘要翻译: 用于分析用于制造集成电路的样本的方法,例如通常称为DRAMS的动态随机存取存储器件。 该方法还提供了包括厚度,宽度和长度的集成芯片。 在具体实施例中,集成芯片具有穿过厚度的一部分的至少一个细长结构,同时垂直于宽度和长度。 在具体实施例中,细长结构具有延伸穿过厚度的垂直部分的结构宽度和结构长度。 该方法包括以垂直于结构长度的定向方式从该厚度的一部分去除集成电路芯片的切片。 在一个具体的实施例中,切片沿着结构长度通过整个一个细长结构提供,以使切片的厚度的一部分提供细长结构,使其具有基本均匀的样本厚度。 该方法还包括使用透射电子通过片的一部分捕获一个或多个图像

    Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits
    3.
    发明授权
    Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits 有权
    在制造集成电路中处理螺旋电子光谱仪(AES)样品的方法

    公开(公告)号:US07504269B2

    公开(公告)日:2009-03-17

    申请号:US11378400

    申请日:2006-03-16

    IPC分类号: G01R31/26

    CPC分类号: G01N23/2276 H01L22/12

    摘要: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

    摘要翻译: 用于分析用于制造集成电路的样品的方法,例如, MOS晶体管,专用集成电路,存储器件,微处理器,片上系统。 该方法包括提供集成电路芯片,其具有至少一个感兴趣区域的表面区域,例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层,而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

    Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits
    4.
    发明授权
    Method for treatment of samples for auger electronic spectrometer (AES) in the manufacture of integrated circuits 有权
    在制造集成电路中处理螺旋电子光谱仪(AES)样品的方法

    公开(公告)号:US07927893B2

    公开(公告)日:2011-04-19

    申请号:US12364977

    申请日:2009-02-03

    IPC分类号: H01L21/66

    CPC分类号: G01N23/2276 H01L22/12

    摘要: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

    摘要翻译: 用于分析用于制造集成电路的样品的方法,例如, MOS晶体管,专用集成电路,存储器件,微处理器,片上系统。 该方法包括提供集成电路芯片,其具有至少一个感兴趣区域的表面区域,例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层,而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

    Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits
    5.
    发明申请
    Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits 有权
    用于俄罗斯电子光谱仪(AES)在集成电路制造中的处理方法

    公开(公告)号:US20090305440A1

    公开(公告)日:2009-12-10

    申请号:US12364977

    申请日:2009-02-03

    IPC分类号: H01L21/66 C23C14/34

    CPC分类号: G01N23/2276 H01L22/12

    摘要: A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis.

    摘要翻译: 用于分析用于制造集成电路的样品的方法,例如, MOS晶体管,专用集成电路,存储器件,微处理器,片上系统。 该方法包括提供集成电路芯片,其具有至少一个感兴趣区域的表面区域,例如接合焊盘。 该方法包括使用阻挡材料覆盖包括感兴趣区域的表面区域的第一部分。 该方法还在表面区域的第二部分上形成金属层,而阻挡材料保护第一部分。 该方法去除阻挡材料以暴露包括感兴趣区域的表面区域的第一部分。 该方法还使金属层进行电压差以从表面区域的第一部分抽出一个或多个带电粒子。 该方法还将包括感兴趣区域的表面区域进行光谱仪分析。

    Method and device for encoding and decoding parameter sets at slice level

    公开(公告)号:US10298946B2

    公开(公告)日:2019-05-21

    申请号:US14355785

    申请日:2012-07-24

    申请人: Ming Li Ping Wu

    发明人: Ming Li Ping Wu

    摘要: Provided is a method for encoding parameter sets at slice level. The method includes: when there are one or more parameter sets, in which the coding tool parameters are identical to the coding tool parameters of a part of coding tools used for the current slice, in the existing parameter sets, encoding the identifiers of parameter sets into bit-stream of the current slice, wherein a parameter set contains common information of the coding tools used in the process of encoding/decoding slice(s). Correspondingly, also provided is a method for decoding parameter sets at slice level and a device for encoding and decoding parameter sets at slice level, which can make full use of the encoded parameter set information when the slice header refers to a plurality of parameter sets, implement flexible configuration of the coding tools used in the process of encoding/decoding slice(s) and reduce information redundancy.

    General anatomic self-locking plate for medial acetabulum and auxiliary apparatus thereof

    公开(公告)号:US20170181784A1

    公开(公告)日:2017-06-29

    申请号:US15044116

    申请日:2016-02-16

    申请人: Ming Li

    发明人: Ming Li

    IPC分类号: A61B17/80 A61B17/84 A61B17/88

    摘要: A general anatomic self-locking plate for medial acetabulum includes a left plate and a right plate mirrored with respect to the left plate. The right plate is a one-piece and includes a horizontal plate body and a vertical plate body. The horizontal plate body and the vertical plate body form a T shape. A through-hole is provided on the vertical plate body along a length direction thereof. Hole pathways of screw holes in the horizontal plate body lean downwardly along the free end of the horizontal plate body. The self-locking plate further includes stress bridges, automatic reduction holes and temporary positioning holes. An auxiliary apparatus of an anatomic self-locking plate for medial acetabulum includes a locking sleeve, a screw placing sleeve and a pair of gripping pliers. The right plate has excellent reduction and stable fixation, and is beneficial to accurately fix fractures without shaping and cutting during operation.