公开(公告)号：US06274420B1

公开(公告)日：2001-08-14

申请号：US09510786

申请日：2000-02-23

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L218238

CPC分类号： H01L29/665 ,  H01L21/76224

摘要： STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

摘要翻译： 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US06437404B1

公开(公告)日：2002-08-20

申请号：US09636239

申请日：2000-08-10

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L2701

CPC分类号： H01L29/78696 ,  H01L21/26533 ,  H01L21/28079 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78603

摘要： A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.

摘要翻译： 完全耗尽的绝缘体上半导体（SOI）晶体管器件具有SOI衬底，其具有相对于衬底的顶表面具有不均匀深度的掩埋绝缘体层，所述掩埋绝缘体层具有靠近顶表面的较浅部分比 层的深部分。 栅极形成在绝缘体层的顶表面和浅部之间的薄半导体层上。 源极和漏极区域形成在栅极的任一侧上，源极和漏极区域分别位于掩埋绝缘体层的深部之一的顶部。 源极和漏极区域因此具有比薄的半导体层更大的厚度。 形成在源区和漏区的厚硅化物区具有低寄生电阻。 制造晶体管器件的方法包括在SOI衬底上形成虚拟栅极结构，并且使用虚拟栅极结构来控制注入的深度以形成不均匀深度的掩埋绝缘体层。

公开(公告)号：US06420770B1

公开(公告)日：2002-07-16

申请号：US09882244

申请日：2001-06-15

申请人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

发明人： Qi Xiang ,  Wei Long ,  Ming-Ren Lin

IPC分类号： H01L2900

CPC分类号： H01L29/665 ,  H01L21/76224

摘要： STI (Shallow Trench Isolation) structures are fabricated such that leakage current is minimized through a field effect transistor fabricated between the STI structures. The shallow trench isolation structure include a pair of isolation trenches, with each isolation trench being etched through a semiconductor substrate. A first dielectric material fills the pair of isolation trenches and extends from the isolation trenches such that sidewalls of the first dielectric material filling the isolation trenches are exposed beyond the top of the semiconductor substrate. A second dielectric material is deposited on the sidewalls of the first dielectric material exposed beyond the top of the semiconductor substrate. The second dielectric material has a different etch rate in an acidic solution from the first dielectric material filling the isolation trenches. The present invention may be used to particular advantage when the first dielectric material filling up the isolation trenches is comprised of silicon dioxide, and when the second dielectric material deposited on the sidewalls of the first dielectric material is comprised of silicon nitride. With the protective silicon nitride covering the sidewalls of the silicon dioxide filling the STI (shallow trench isolation) trenches, formation of divots is avoided in the silicon dioxide filling the STI (shallow trench isolation) trenches. Thus, when a field effect transistor is fabricated between such STI structures, silicides formed near the STI structures do not extend down toward the junction of the drain contact region and the source contact region of the field effect transistor such that drain and source leakage current is minimized.

摘要翻译： 制造STI（浅沟槽隔离）结构，使得通过在STI结构之间制造的场效应晶体管使漏电流最小化。 浅沟槽隔离结构包括一对隔离沟槽，每个隔离沟槽通过半导体衬底被蚀刻。 第一介电材料填充一对隔离沟槽并从隔离沟槽延伸，使得填充隔离沟槽的第一介电材料的侧壁暴露在半导体衬底的顶部之外。 第二电介质材料沉积在暴露于半导体衬底的顶部之外的第一电介质材料的侧壁上。 第二电介质材料在从填充隔离沟槽的第一介电材料的酸性溶液中具有不同的蚀刻速率。 当填充隔离沟槽的第一介电材料由二氧化硅组成并且当沉积在第一介电材料的侧壁上的第二介电材料由氮化硅构成时，本发明可以被用于特别有利。 通过覆盖填充STI（浅沟槽隔离）沟槽的二氧化硅的侧壁的保护性氮化硅，在填充STI（浅沟槽隔离）沟槽的二氧化硅中避免形成纹理。 因此，当在这样的STI结构之间制造场效应晶体管时，形成在STI结构附近的硅化物不会朝向场效应晶体管的漏极接触区域和源极接触区域的接点向下延伸，使得漏极和漏极电流为 最小化。

公开(公告)号：US07422961B2

公开(公告)日：2008-09-09

申请号：US10389456

申请日：2003-03-14

申请人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

发明人： Haihong Wang ,  Minh-Van Ngo ,  Qi Xiang ,  Paul R. Besser ,  Eric N. Paton ,  Ming-Ren Lin

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L29/1054

摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

摘要翻译： 集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。 浅沟槽隔离技术用于应变硅（SMOS）工艺。 用于沟槽的衬垫由半导体或金属层形成，该半导体或金属层在低温过程中沉积，这降低了锗除气。 低温工艺可以是CVD工艺。

公开(公告)号：US20080054316A1

公开(公告)日：2008-03-06

申请号：US11926655

申请日：2007-10-29

申请人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L29/78

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US06858503B1

公开(公告)日：2005-02-22

申请号：US10358484

申请日：2003-02-05

申请人： Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

发明人： Minh V. Ngo ,  Ming-Ren Lin ,  Paul R. Besser ,  Qi Xiang ,  Eric N. Paton ,  Jung-Suk Goo

IPC分类号： H01L21/306 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L21/02046 ,  H01L29/1054

摘要： A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.

摘要翻译： 制造系统利用从晶片顶表面去除锗的方案。 暴露于气体，如含有盐酸的气体，可以从上表面除去锗。 该协议可以允许在Flash产品制造线和应变硅（SMOS）生产线中使用共享设备。 该协议允许在SMOS器件中更好的硅化。

公开(公告)号：US06248675B1

公开(公告)日：2001-06-19

申请号：US09369099

申请日：1999-08-05

申请人： Qi Xiang ,  Ming-Ren Lin

发明人： Qi Xiang ,  Ming-Ren Lin

IPC分类号： H01L21302

CPC分类号： H01L21/02672 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/28061 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

摘要： A method for fabricating short channel field effect transistors with dual gates and with a gate dielectric having a high dielectric constant. The field effect transistor is initially fabricated to have a sacrificial gate dielectric and a dummy gate electrode. Any fabrication process, such as an activation anneal or a salicidation anneal of the source and drain of the field effect transistor, using relatively high temperature is performed with the field effect transistor having the sacrificial gate dielectric and the dummy gate electrode. The dummy gate electrode and the sacrificial gate dielectric are etched from the field effect transistor to form a gate opening. A layer of dielectric with high dielectric constant is deposited on the side wall and the bottom wall of the gate opening, and a crystallization enhancing layer is deposited on the bottom wall of the gate opening. Amorphous gate electrode material, such as amorphous silicon, is deposited to fill the gate opening after the crystallization enhancing layer has been deposited. Dual gates for both an N-channel field effect transistor and a P-channel field effect transistor are formed by doping the amorphous gate electrode material with an N-type dopant for an N-channel field effect transistor, and by doping the amorphous gate electrode material with a P-type dopant for a P-channel field effect transistor. The amorphous gate electrode material in the gate opening is then annealed at a relatively low temperature, such as 500° Celsius, using an enhanced crystallization process to convert the amorphous gate electrode material, such as amorphous silicon, into polycrystalline gate electrode material, such as polycrystalline silicon. Thus, relatively low temperatures are used in the present invention to preserve the integrity of the gate dielectric having the high dielectric constant.

摘要翻译： 一种用于制造具有双栅极和具有高介电常数的栅极电介质的短沟道场效应晶体管的方法。 场效应晶体管最初被制造成具有牺牲栅极电介质和虚拟栅电极。 使用具有牺牲栅极电介质和虚拟栅电极的场效应晶体管，使用相对较高的温度进行任何制造工艺，例如场效应晶体管的源极和漏极的激活退火或腐蚀退火。 从场效应晶体管蚀刻伪栅电极和牺牲栅电介质以形成栅极开口。 在栅极的侧壁和底壁上沉积具有高介电常数的电介质层，并且在栅极开口的底壁上沉积结晶增强层。 沉积结晶增强层之后，沉积非晶态栅极材料，例如非晶硅，以填充栅极开口。 通过用N型掺杂剂掺杂非晶栅电极材料来形成用于N沟道场效应晶体管和P沟道场效应晶体管的双栅极，并且通过掺杂非晶栅电极 具有用于P沟道场效应晶体管的P型掺杂剂的材料。 然后使用增强的结晶工艺在较低温度（例如500℃）下将栅极开口中的非晶栅电极材料退火，以将诸如非晶硅的非晶栅电极材料转化为多晶栅电极材料，例如 多晶硅。 因此，在本发明中使用相对较低的温度来保持具有高介电常数的栅极电介质的完整性。

公开(公告)号：US6165902A

公开(公告)日：2000-12-26

申请号：US187520

申请日：1998-11-06

申请人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

发明人： Shekhar Pramanick ,  Ming-Ren Lin ,  Qi Xiang

IPC分类号： H01L21/285 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/28568

摘要： Low resistance contacts are formed on source/drain regions and gate electrodes by selectively depositing a reaction barrier layer and selectively depositing a metal layer on the reaction barrier layer. Embodiments include selectively depositing an alloy of cobalt and tungsten which functions as a reaction barrier layer preventing silicidation of a layer of nickel or cobalt selectively deposited thereon. Embodiments also include tailoring the composition of the cobalt tungsten alloy so that a thin silicide layer is formed thereunder for reduced contact resistance.

摘要翻译： 通过选择性地沉积反应阻挡层并在反应阻挡层上选择性地沉积金属层，在源/漏区和栅电极上形成低电阻触点。 实施方案包括选择性沉积钴和钨的合金，其用作反应阻挡层，防止选择性沉积在其上的镍或钴层的硅化。 实施例还包括定制钴钨合金的组成，使得在其下形成薄的硅化物层以降低接触电阻。

公开(公告)号：US6093594A

公开(公告)日：2000-07-25

申请号：US69879

申请日：1998-04-29

申请人： Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

发明人： Geoffrey Choh-Fei Yeap ,  Qi Xiang ,  Ming-Ren Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864

摘要： An ultra-large scale CMOS integrated circuit semiconductor device is processed after the formation of the gates and gate oxides by N-type dopant implantation to form N-type shallow source and drain extension junctions. Spacers are formed for N-type dopant implantation to form N-type deep source and drain junctions. A higher temperature rapid thermal anneal then optimizes the NMOS source and drain extension junctions and junctions, and the spacers are removed. A thin oxide spacer is used to displace P-type dopant implantation to P-type shallow source and drain extension junctions. A nitride spacer is then formed for P-type dopant implantation to form P-type deep source and drain junctions. A second lower temperature rapid thermal anneal then independently optimizes the PMOS source and drain junctions independently from the NMOS source and drain junctions.

摘要翻译： 在通过N型掺杂剂注入形成栅极和栅极氧化物之后，处理超大规模CMOS集成电路半导体器件，以形成N型浅源极和漏极延伸结。 形成N型掺杂剂注入以形成N型深源极和漏极结的间隔物。 然后，较高温度的快速热退火优化NMOS源极和漏极延伸接合点和结，并且去除间隔物。 使用薄氧化物间隔物将P型掺杂剂注入位移到P型浅源极和漏极延伸结。 然后形成用于P型掺杂剂注入以形成P型深源极和漏极结的氮化物间隔物。 然后，第二较低温度的快速热退火独立地优化PMOS源极和漏极结，这些独立于NMOS源极和漏极结。

公开(公告)号：US5960322A

公开(公告)日：1999-09-28

申请号：US994308

申请日：1997-12-19

申请人： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

发明人： Qi Xiang ,  Geoffrey Yeap ,  Srinath Krishnan ,  Ming-Ren Lin

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6656 ,  Y10S438/917

摘要： A method in the manufacture of ultra-large scale integrated circuit semiconductor devices suppresses boron loss due to segregation into the screen oxide during the boron activation rapid thermal anneal. A nitridation of the screen oxide is used to incorporate nitrogen into the screen oxide layer prior to boron implantation for ultra-shallow, source and drain extension junctions. A second nitridation of a second screen oxide is used prior to boron implantation for deeper, source and drain junctions. This method significantly suppresses boron diffusion and segregation away from the silicon substrate which reduces series resistance of the complete source and drain junctions.

摘要翻译： 制造超大规模集成电路半导体器件的方法抑制了硼激活快速热退火期间由于偏析到屏幕氧化物中的硼损失。 在用于超浅，源极和漏极延伸结的硼注入之前，使用屏幕氧化物的氮化将氮掺入屏幕氧化物层中。 在硼注入之前，使用第二屏蔽氧化物的第二次氮化用于更深，源极和漏极结。 该方法显着抑制了硼扩散和离开硅衬底的偏析，从而降低了整个源极和漏极结的串联电阻。