公开(公告)号：US20220373407A1

公开(公告)日：2022-11-24

申请号：US17326544

申请日：2021-05-21

Applicant: QUANTA COMPUTER INC.

Inventor： Hsiao-Tsu NI ,  Ying-Che CHANG ,  Chao-Nan LIN

IPC: G01K11/00 ,  H05K7/04 ,  H05K1/18

Abstract: A system includes a first printed circuit board (PCB), a temperature sensor, a switching circuit provided on the first PCB, and a controller. The temperature sensor is configured to measure temperature of at least an area of the first PCB. The controller is configured to trigger the switching circuit to turn off power to the first PCB, based at least in part on the temperature sensor detecting a temperature above a temperature threshold. The system is able to disrupt power much faster than conventional methods of power protection which may have a blind spot to certain areas of the first PCB, since these methods rely on power disruption when a maximum power is sensed.

公开(公告)号：US20220408590A1

公开(公告)日：2022-12-22

申请号：US17349715

申请日：2021-06-16

Applicant: Quanta Computer Inc.

Inventor： Hsien-Yang CHENG ,  Ying-Che CHANG ,  Yi-An CHEN ,  Yu-Tang ZENG

IPC: H05K7/20 ,  G06F1/20

Abstract: A hardware-based fan controller for controlling fan modules in a computer system having multiple computer nodes is disclosed. Each of the computer nodes has a service processor. The fan controller includes a slave module that receives fan speed commands from each of the service processors. A fan speed generator is coupled to the slave module and a subset of the fan modules. The fan speed generator receives fan speed commands from the slave module and fan speed outputs from the subset of fan modules. The fan speed generator is configured to output a speed command to each of the fan modules in the subset.

公开(公告)号：US20220350386A1

公开(公告)日：2022-11-03

申请号：US17243220

申请日：2021-04-28

Applicant: Quanta Computer Inc.

Inventor： Hsien-Yang CHENG ,  Ying-Che CHANG ,  Ya-Chau YANG

IPC: G06F1/26 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G05B19/042

Abstract: A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

公开(公告)号：US20190286590A1

公开(公告)日：2019-09-19

申请号：US15921092

申请日：2018-03-14

Applicant: QUANTA COMPUTER INC.

Inventor： Chi-Tsun CHOU ,  Ying-Che CHANG ,  Yen-Tse CHANG ,  Wen-Hua LO

IPC: G06F13/362 ,  G06F13/42 ,  G06F1/28

Abstract: An example multi-node system that prevents multi-master issues on a common bus is disclosed. The system has a first node and a second node. A backplane is coupled to the first and second nodes via a system management bus. A complex programmable logic device is coupled to the system management bus. The complex programmable logic device includes hardware logic operable to arbitrate between bus commands from the first and second nodes.

公开(公告)号：US20190236277A1

公开(公告)日：2019-08-01

申请号：US15886425

申请日：2018-02-01

Applicant: QUANTA COMPUTER INC.

Inventor： Ying-Che CHANG ,  Kung-Lung TSAI ,  Wen-Hua LO ,  Chung-Hung TSAI

IPC: G06F21/57 ,  G06F8/654 ,  G06F21/64

CPC classification number: G06F21/572 ,  G06F8/654 ,  G06F11/1417 ,  G06F11/1433 ,  G06F11/1441 ,  G06F21/64

Abstract: A system and method for automatic recovery of a firmware image is disclosed. The method can include creating a shadow firmware image in a storage device from a firmware image in non-volatile memory. It is determined whether an abnormal event affecting the firmware image has occurred. The shadow firmware image is recovered from the storage device. The shadow firmware image is copied to the non-volatile memory.

公开(公告)号：US20190220340A1

公开(公告)日：2019-07-18

申请号：US15944139

申请日：2018-04-03

Applicant: QUANTA COMPUTER INC.

Inventor： Chi-Tsun CHOU ,  Ying-Che CHANG ,  Yen-Tse CHANG

IPC: G06F11/07 ,  G06F11/34 ,  G06F11/30 ,  G06F11/14

CPC classification number: G06F11/0757 ,  G06F11/1441 ,  G06F11/3058

Abstract: The present disclosure provides a system and method for resetting a hang-up baseboard management controller (BMC), or another component of a server system using a hardware watch-dog-timer (HW WDT) circuit and/or complex programmable logic device (CPLD). The HW WDT circuit can monitor heartbeat signals from the BMC, and determine the health condition of the BMC. In an event that the BMC's health condition fails to meet a predefined criterion, the HW WDT circuit generates a reset signal to reset the BMC. The CPLD can collect from the BMC, health information of components of the server system. The CPLD can also collect the BMC's health condition from the HW WDT circuit. Upon determining which specific component of the server system hangs up, the CPLD can generate a reset signal to reset the specific component.