Abstract:
A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.
Abstract:
A signal combining circuit supplied current to both amplifiers of a first differential amplifier and to an error voltage storage circuit. The first differential amplifier is controlled by the difference between a first input waveform and its average value or a reference value and this difference results in charging and discharging of the error voltage storage circuit to raise and lower its voltage respectively. A second differential amplifier alternately keys the first differential amplifier into conduction in response to a second input waveform to update the error voltage and subtracts the output current from the signal combining circuit to shut off the first differential amplifier and hold the error voltage in a high impedance circuit until the next updating period.
Abstract:
A protection circuit limits the collector current of a transistor employed as a clamp-to-ground stage in the event the collector terminal of the transistor is accidentally short circuited during conduction to a low-impedance voltage source. The protection circuit includes a transistor which has its baseemitter junction coupled across the base-emitter junction of the clamping transistor and has a collector resistor chosen to provide a saturation current for the protection transistor which holds the base-emitter junction voltage at a level which limits the collector current of the clamping transistor.
Abstract:
A sample-and-hold circuit employs first and second transistors having serially coupled collector-to-emitter current paths and including a negative feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for driving, for example, a capacitive load. The detector is keyed by means of a single keying transistor which provides a conduction path from the collector and the base of the first transistor to ground. Diodes coupled in series with the keying transistor and both the base and the collector of the first transistor insure that the first and second transistors are switched in and out of conduction simultaneously. The circuit may be employed as a phase comparator.
Abstract:
Semiconductor voltage follower arrangements adapted for construction in integrated circuit form. A load circuit is coupled to the emitter of a voltage follower transistor. Operating potential is supplied to the collector of the follower transistor via the base-emitter circuit of a second transistor arranged in a common emitter transistor. The collector-emitter circuit of a regulator transistor is coupled across the load circuit. Feedback is provided from the output of the common emitter transistor to the input of the regulator transistor such that the collector current of the follower transistor is substantially independent of input voltage variations applied to the base of the follower transistor.
Abstract:
A signal translating circuit includes a constant current transistor, a variable conduction transistor having a signal input terminal, and a feedback loop coupling the transistors. The collector-emitter paths of the transistors are connected in series across a voltage source. An output transistor is electrically and thermally coupled to the variable conduction transistor to provide an output current which is proportional to and at a predetermined phase relationship with the input current. The circuit is characterized by having both a low impedance current input, and a high impedance voltage input. The direct voltage level of the input can be selected for suitable biasing of the preceding stage. The circuit can be employed, for example, as a current sampler, a linear amplifier, a Q-multiplier, or a signal-matrixing circuit.
Abstract:
A high-gain, linear, differential amplifier which provides output voltage variations substantially equal to the total supply voltage associated with the amplifier. Each half of the amplifier comprises an input transistor, a shunt regulator transistor and a feedback arrangement between input and regulator transistors to maintain substantially constant current in the input transistor. Output transistors having their inputs in parallel with the regulator transistor inputs and output loads coupled in their collector-emitter current paths are provided.
Abstract:
A hysteresis voltage switch is coupled between a direct current supply voltage and a source of deflection synchronizing waveforms. The source of deflection synchronizing waveforms is operable when the supply voltage reaches a minimum amplitude. The switch does not close to couple the deflection synchronizing waveform generator to the supply voltage, however, until the supply voltage is substantially in excess of the minimum amplitude. Cycling off and on of the deflection synchronizing waveform generator as a result of reduction in the supply voltage when the deflection output stages draw current from the supply is thereby prevented.
Abstract:
An electrical circuit including a resistor, a voltage source and a temperature independent voltage divider arrangement, the voltage divider including semiconductor amplifying devices for coupling the source across the resistor and being arranged such that the temperature variation of the resistor value and that of the divided voltage impressed across the resistor are substantially equal to provide a temperature compensated, substantially constant current through the resistor. The desired output current is provided from a relatively high source impedance by means of one of the semiconductor devices of the divider or by means of an additional semiconductor device.
Abstract:
A semiconductor P-N junction voltage source temperature compensating network comprises a resistor coupled in parallel with a resistor and a semiconductor P-N junction device in series. The parallel combination is coupled across the terminals of a semiconductor P-N junction voltage source. The source voltage varies with temperature and current according to the diode equations. The voltage across the series coupled P-N junction device varies in the same manner, decreasing with increasing temperature over a substantial range of operating temperature so that the effective resistance of the series combination decreases in substantially direct proportion to the source voltage. Thus if the resistors in the parallel circuit are chosen according to a specific ratio a substantially constant current relatively independent of temperature over a broad range of operating temperature can be made to flow through the parallel combination.