Dual mode deflection synchronizing system
    1.
    发明授权
    Dual mode deflection synchronizing system 失效
    双模偏转同步系统

    公开(公告)号:US3899635A

    公开(公告)日:1975-08-12

    申请号:US43804774

    申请日:1974-01-30

    Applicant: RCA CORP

    CPC classification number: H04N5/12

    Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.

    Abstract translation: 双模偏转同步系统包括可复位计数器,该计数器产生无噪声的内部同步信号和表示在计数器被正确同步的情况下应当接收外部垂直同步信号的间隔的信号。 同步信号验证检测器耦合到外部垂直同步信号源和模式开关,使得如果外部信号在由该同步信号验证检测器确定的该预测间隔期间到达,则系统在其同步模式下继续工作 内部产生的同步信号。 如果外部信号在该预测间隔期间未到达,则模式切换将系统切换到非同步模式。 也耦合到外部同步信号源和模式开关的垂直同步信号检测器开始搜索具有真实外部同步信号的持续时间特性的外部信号。 在接收到这样的信号之前,系统通过可复位计数器产生的内部同步信号继续同步。 当接收到这样的信号时,垂直同步信号检测器复位计数器以校正其与所接收的外部垂直同步信号的同步,并且切换模式开关以将系统返回到其同步操作模式。

    Current output frequency and phase comparator
    2.
    发明授权
    Current output frequency and phase comparator 失效
    电流输出频率和相位比较器

    公开(公告)号:US3863080A

    公开(公告)日:1975-01-28

    申请号:US40776273

    申请日:1973-10-18

    Applicant: RCA CORP

    CPC classification number: H03L7/091 H03F3/72 H04N5/04 H04N5/123 H04N5/126

    Abstract: A signal combining circuit supplied current to both amplifiers of a first differential amplifier and to an error voltage storage circuit. The first differential amplifier is controlled by the difference between a first input waveform and its average value or a reference value and this difference results in charging and discharging of the error voltage storage circuit to raise and lower its voltage respectively. A second differential amplifier alternately keys the first differential amplifier into conduction in response to a second input waveform to update the error voltage and subtracts the output current from the signal combining circuit to shut off the first differential amplifier and hold the error voltage in a high impedance circuit until the next updating period.

    Abstract translation: 信号组合电路将电流提供给第一差分放大器的两个放大器和误差电压存储电路。 第一差分放大器由第一输入波形与其平均值或参考值之间的差值控制,并且该差异导致误差电压存储电路的充放电分别升高和降低。 第二差分放大器响应于第二输入波形交替地将第一差分放大器按键导通,以更新误差电压,并从信号组合电路中减去输出电流以切断第一差分放大器并将误差电压保持在高阻抗 直到下一个更新周期。

    Protection circuit
    3.
    发明授权
    Protection circuit 失效
    保护电路

    公开(公告)号:US3641361A

    公开(公告)日:1972-02-08

    申请号:US3641361D

    申请日:1970-12-03

    Applicant: RCA CORP

    CPC classification number: H03K4/64 H02H7/20 H03K4/085

    Abstract: A protection circuit limits the collector current of a transistor employed as a clamp-to-ground stage in the event the collector terminal of the transistor is accidentally short circuited during conduction to a low-impedance voltage source. The protection circuit includes a transistor which has its baseemitter junction coupled across the base-emitter junction of the clamping transistor and has a collector resistor chosen to provide a saturation current for the protection transistor which holds the base-emitter junction voltage at a level which limits the collector current of the clamping transistor.

    Abstract translation: 如果晶体管的集电极在导通到低阻抗电压源时意外短路,则保护电路会限制用作钳位到地电平的晶体管的集电极电流。 保护电路包括晶体管,其晶体管的基极 - 发射极结耦合在钳位晶体管的基极 - 发射极结之间,并且具有集电极电阻,其被选择为保护晶体管提供饱和电流,保护晶体管将基极 - 发射极结电压保持在一定水平 这限制了钳位晶体管的集电极电流。

    Sample-and-hold circuit
    4.
    发明授权
    Sample-and-hold circuit 失效
    样品保持电路

    公开(公告)号:US3641258A

    公开(公告)日:1972-02-08

    申请号:US3641258D

    申请日:1970-06-29

    Applicant: RCA CORP

    CPC classification number: H03D13/006

    Abstract: A sample-and-hold circuit employs first and second transistors having serially coupled collector-to-emitter current paths and including a negative feedback path coupling the collector of the first transistor to the base of the second transistor to provide a high-input impedance and a relatively low-output impedance circuit suitable for driving, for example, a capacitive load. The detector is keyed by means of a single keying transistor which provides a conduction path from the collector and the base of the first transistor to ground. Diodes coupled in series with the keying transistor and both the base and the collector of the first transistor insure that the first and second transistors are switched in and out of conduction simultaneously. The circuit may be employed as a phase comparator.

    Abstract translation: 采样和保持电路采用具有串联耦合集电极到发射极电流路径的第一和第二晶体管,并且包括将第一晶体管的集电极耦合到第二晶体管的基极的负反馈路径,以提供高输入阻抗, 适用于驱动例如电容性负载的相对低输出的阻抗电路。 检测器通过单个键控晶体管键控,该晶体管提供从第一晶体管的集电极和基极到地的导电路径。 与键控晶体管和第一晶体管的基极和集电极串联耦合的二极管确保第一和第二晶体管同时被导通和断开。 电路可以用作相位比较器。

    Electronic signal amplifier
    5.
    发明授权
    Electronic signal amplifier 失效
    电子信号放大器

    公开(公告)号:US3701032A

    公开(公告)日:1972-10-24

    申请号:US3701032D

    申请日:1971-02-16

    Applicant: RCA CORP

    Abstract: Semiconductor voltage follower arrangements adapted for construction in integrated circuit form. A load circuit is coupled to the emitter of a voltage follower transistor. Operating potential is supplied to the collector of the follower transistor via the base-emitter circuit of a second transistor arranged in a common emitter transistor. The collector-emitter circuit of a regulator transistor is coupled across the load circuit. Feedback is provided from the output of the common emitter transistor to the input of the regulator transistor such that the collector current of the follower transistor is substantially independent of input voltage variations applied to the base of the follower transistor.

    Abstract translation: 适用于集成电路形式的半导体电压跟随器结构。 负载电路耦合到电压跟随器晶体管的发射极。 工作电位通过布置在公共发射极晶体管中的第二晶体管的基极 - 发射极电路提供给跟随晶体管的集电极。 调节晶体管的集电极 - 发射极电路跨过负载电路耦合。 从公共发射极晶体管的输出到稳压晶体管的输入提供反馈,使得跟随晶体管的集电极电流基本上与施加到跟随晶体管的基极的输入电压变化无关。

    Transistor signal translating stage
    6.
    发明授权
    Transistor signal translating stage 失效
    晶体管信号转换阶段

    公开(公告)号:US3641448A

    公开(公告)日:1972-02-08

    申请号:US3641448D

    申请日:1969-10-01

    Applicant: RCA CORP

    CPC classification number: H03F3/45197 H03F1/56 H03F3/347 H03F3/45098

    Abstract: A signal translating circuit includes a constant current transistor, a variable conduction transistor having a signal input terminal, and a feedback loop coupling the transistors. The collector-emitter paths of the transistors are connected in series across a voltage source. An output transistor is electrically and thermally coupled to the variable conduction transistor to provide an output current which is proportional to and at a predetermined phase relationship with the input current. The circuit is characterized by having both a low impedance current input, and a high impedance voltage input. The direct voltage level of the input can be selected for suitable biasing of the preceding stage. The circuit can be employed, for example, as a current sampler, a linear amplifier, a Q-multiplier, or a signal-matrixing circuit.

    High-gain differential amplifier
    7.
    发明授权
    High-gain differential amplifier 失效
    高增益差分放大器

    公开(公告)号:US3622903A

    公开(公告)日:1971-11-23

    申请号:US3622903D

    申请日:1969-12-29

    Applicant: RCA CORP

    CPC classification number: H03F3/45197 H03F1/56 H03F3/347 H03F3/45098

    Abstract: A high-gain, linear, differential amplifier which provides output voltage variations substantially equal to the total supply voltage associated with the amplifier. Each half of the amplifier comprises an input transistor, a shunt regulator transistor and a feedback arrangement between input and regulator transistors to maintain substantially constant current in the input transistor. Output transistors having their inputs in parallel with the regulator transistor inputs and output loads coupled in their collector-emitter current paths are provided.

    Abstract translation: 信号转换电路包括恒流晶体管,具有信号输入端的可变导体晶体管和耦合晶体管的反馈回路。 晶体管的集电极 - 发射极路径跨越电压源串联连接。 输出晶体管电耦合到可变导电晶体管,以提供与输入电流成比例并且与预定相位关系的输出电流。 该电路的特征在于具有低阻抗电流输入和高阻抗电压输入。 可以选择输入的直流电压,以适应前一级的偏置。 该电路可以用作例如电流取样器,线性放大器,Q倍增器或信号矩阵电路。

    Hysteresis voltage supply for deflection synchronizing waveform generator
    8.
    发明授权
    Hysteresis voltage supply for deflection synchronizing waveform generator 失效
    偏转同步波形发生器的滞后电压

    公开(公告)号:US3898525A

    公开(公告)日:1975-08-05

    申请号:US49622474

    申请日:1974-08-09

    Applicant: RCA CORP

    CPC classification number: H04N3/20 H03K3/2893 H04N3/16 H04N5/44

    Abstract: A hysteresis voltage switch is coupled between a direct current supply voltage and a source of deflection synchronizing waveforms. The source of deflection synchronizing waveforms is operable when the supply voltage reaches a minimum amplitude. The switch does not close to couple the deflection synchronizing waveform generator to the supply voltage, however, until the supply voltage is substantially in excess of the minimum amplitude. Cycling off and on of the deflection synchronizing waveform generator as a result of reduction in the supply voltage when the deflection output stages draw current from the supply is thereby prevented.

    Abstract translation: 滞后电压开关耦合在直流电源电压和偏转同步波形源之间。 当电源电压达到最小幅度时,偏转同步波形的源可以工作。 然而,开关不接近将偏转同步波形发生器耦合到电源电压,直到电源电压基本上超过最小幅度。 因此,防止偏转输出级从电源中抽出电流时,由于减小电源电压,偏转同步波形发生器的周期和周期。

    Electric circuit for providing temperature compensated current
    9.
    发明授权
    Electric circuit for providing temperature compensated current 失效
    提供温度补偿电流的电路

    公开(公告)号:US3895286A

    公开(公告)日:1975-07-15

    申请号:US10462771

    申请日:1971-01-07

    Applicant: RCA CORP

    CPC classification number: G05F3/18 G05F1/562

    Abstract: An electrical circuit including a resistor, a voltage source and a temperature independent voltage divider arrangement, the voltage divider including semiconductor amplifying devices for coupling the source across the resistor and being arranged such that the temperature variation of the resistor value and that of the divided voltage impressed across the resistor are substantially equal to provide a temperature compensated, substantially constant current through the resistor. The desired output current is provided from a relatively high source impedance by means of one of the semiconductor devices of the divider or by means of an additional semiconductor device.

    Abstract translation: 一种包括电阻器,电压源和独立于温度的分压器装置的电路,所述分压器包括用于将电源跨过电阻器耦合的半导体放大装置,并且被布置成使得电阻器值和分压电压的温度变化 通过电阻器施加的电压基本上等于通过电阻器提供温度补偿的基本上恒定的电流。 期望的输出电流通过分压器的半导体器件之一或借助附加的半导体器件由较高的源极阻抗提供。

    V' be 'voltage voltage source temperature compensation network
    10.
    发明授权
    V' be 'voltage voltage source temperature compensation network 失效
    V'BE'电压源温度补偿网络

    公开(公告)号:US3886435A

    公开(公告)日:1975-05-27

    申请号:US38527173

    申请日:1973-08-03

    Applicant: RCA CORP

    CPC classification number: G05F3/265 Y10S323/901 Y10S323/907

    Abstract: A semiconductor P-N junction voltage source temperature compensating network comprises a resistor coupled in parallel with a resistor and a semiconductor P-N junction device in series. The parallel combination is coupled across the terminals of a semiconductor P-N junction voltage source. The source voltage varies with temperature and current according to the diode equations. The voltage across the series coupled P-N junction device varies in the same manner, decreasing with increasing temperature over a substantial range of operating temperature so that the effective resistance of the series combination decreases in substantially direct proportion to the source voltage. Thus if the resistors in the parallel circuit are chosen according to a specific ratio a substantially constant current relatively independent of temperature over a broad range of operating temperature can be made to flow through the parallel combination.

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