公开(公告)号：US20190140867A1

公开(公告)日：2019-05-09

申请号：US15975821

申请日：2018-05-10

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： SHIH-HUNG WANG ,  SHEN-KUO HUANG ,  GERCHIH CHOU ,  WEN-SHAN WANG

IPC分类号： H04L25/02 ,  H03H11/30 ,  H03H7/40 ,  G11C16/26 ,  G11C7/22 ,  H05K1/14

CPC分类号： H04L25/0278 ,  G06F13/16 ,  G06F13/1668 ,  G06F13/4086 ,  G11C7/1057 ,  G11C7/222 ,  G11C16/26 ,  H03H7/40 ,  H03H11/30 ,  H05K1/141

摘要： A memory controller adjusts impedance matching of an output terminal and outputs a control signal that controls a memory through the output terminal. The memory controller includes a first driving and impedance matching circuit, a second driving and impedance matching circuit, and a logic circuit. The logic circuit, which is coupled to the first driving and impedance matching circuit and the second driving and impedance matching circuit, sets a first impedance and a first driving capability of the first driving and impedance matching circuit, sets a second impedance and a second driving capability of the second driving and impedance matching circuit, and enables the first driving and impedance matching circuit to cause the control signal to have a first level or enables the second driving and impedance matching circuit to cause the control signal to have a second level different from the first level.

公开(公告)号：US20200142844A1

公开(公告)日：2020-05-07

申请号：US16182680

申请日：2018-11-07

申请人： REALTEK SEMICONDUCTOR CORPORATION

发明人： KUO-WEI CHI ,  CHUN-CHI YU ,  CHIH-WEI CHANG ,  GERCHIH CHOU ,  SHIH-CHANG CHEN

IPC分类号： G06F13/16 ,  G06F3/06 ,  G11C7/22

摘要： Disclosed is a DDR SDRAM physical layer interface circuit including: a multiphase clock generator generating a plurality of clocks including a reference clock, a first clock, a second clock and a third clock; a frequency dividing circuit generating a PHY clock according to the first clock; a clock output path outputting the reference clock to a storage circuit; a first output circuit outputting a first output signal to the storage circuit according to a first input signal of a memory controller, the first clock and the PHY clock; a second output circuit outputting a second output signal to the storage circuit according to a second input signal of the memory controller, the second clock and the PHY clock; and a third output circuit outputting a third output signal to the storage circuit according to a third input signal of the memory controller, the third clock and the PHY clock.