公开(公告)号：US20140284818A1

公开(公告)日：2014-09-25

申请号：US14294978

申请日：2014-06-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi ABEMATSU ,  Takafumi BETSUI ,  Atsushi KURODA

IPC: H01L23/00 ,  H01L23/12

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/04 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.