公开(公告)号：US12132029B2

公开(公告)日：2024-10-29

申请号：US17648161

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chia Hu ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/03 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/94 ,  H01L25/03 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73259 ,  H01L2224/80895 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/94 ,  H01L2224/80

Abstract: A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US20240234369A1

公开(公告)日：2024-07-11

申请号：US18617113

申请日：2024-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokgeun AHN

IPC: H01L25/065 ,  H01L23/13 ,  H01L25/18

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L25/18 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: A semiconductor package is provided. The semiconductor package includes: a package substrate having a first surface, a second surface that is provided opposite the first surface and has a concave portion, and a through-hole having a side surface that is oblique with respect to the first surface, and a first diameter of a first opening of the through-hole defined through the first surface being less than a second diameter of a second opening of the through-hole defined through a bottom surface of the concave portion; a plurality of first semiconductor chips provided on the first surface; a second semiconductor chip provided on the bottom surface; and a molding portion provided in the through-hole, and covering the plurality of first semiconductor chips and the second semiconductor chip.

公开(公告)号：US11848310B2

公开(公告)日：2023-12-19

申请号：US17391287

申请日：2021-08-02

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Won Geol Lee ,  Won Chul Do ,  Ji Hun Yi

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/50 ,  H01L23/49811 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582

Abstract: Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

公开(公告)号：US11804457B2

公开(公告)日：2023-10-31

申请号：US17219905

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00 ,  H01Q1/22 ,  H01L21/683 ,  H01Q21/00

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01Q1/2283 ,  H01Q21/0087 ,  H01L23/5385 ,  H01L25/0655 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06586

Abstract: A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The first die, the second die and the third die are molded in a molding compound. The first redistribution layer is disposed on the molding compound and is electrically connected to the first die, the second die and the third die. The antenna is located on the molding compound and electrically connected to the first die, the second die and the third die, wherein a distance of an electrical connection path between the first die and the antenna is smaller than or equal to a distance of an electrical connection path between the second die and the antenna and a distance of an electrical connection path between the third die and the antenna. The conductive elements are connected to the first redistribution layer, wherein the first redistribution layer is located between the conductive elements and the molding compound.

公开(公告)号：US11791315B2

公开(公告)日：2023-10-17

申请号：US17520568

申请日：2021-11-05

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay ,  Eiichi Nakano

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H05K1/02

CPC classification number: H01L25/0657 ,  H01L23/3738 ,  H01L23/49877 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H05K1/0207 ,  H01L2224/16235 ,  H01L2224/17519 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/06589 ,  H05K2201/066 ,  H05K2201/10159

Abstract: Semiconductor assemblies including thermal layers and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise one or more semiconductor devices over a substrate. The substrate includes a thermal layer configured to transfer thermal energy across the substrate. The thermal energy is transferred from the semiconductor device to the graphene layer using one or more thermal connectors.

公开(公告)号：US11657868B2

公开(公告)日：2023-05-23

申请号：US17540950

申请日：2021-12-02

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C5/02 ,  G11C11/4093 ,  G11C11/4096 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0401 ,  H01L2924/00011 ,  H01L2224/0401

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20190221249A1

公开(公告)日：2019-07-18

申请号：US16211966

申请日：2018-12-06

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C11/406 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48

CPC classification number: G11C11/4093 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/481 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US20190013294A1

公开(公告)日：2019-01-10

申请号：US16056250

申请日：2018-08-06

Applicant: Micron Technology, Inc.

Inventor： Dai Sasaki ,  Mitsuaki Katagiri ,  Satoshi Isa

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L23/525 ,  H01L23/528 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02371 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06138 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2224/45099

Abstract: Some embodiments include an apparatus having a first chip and a second chip. Each of the first and second chips comprises a multilevel wiring structure and a redistribution wiring layer over the multilevel wiring structure. The redistribution wiring layers include redistribution wiring and pads electrically coupled to the redistribution wiring. The first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip. The pad of the first chip faces the pad of the second chip, and is vertically spaced from the pad of the second chip by an intervening insulative region. The redistribution wiring of the second chip is electrically coupled to the redistribution wiring of the first chip through a bonding region.

公开(公告)号：US10074632B2

公开(公告)日：2018-09-11

申请号：US15147922

申请日：2016-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sub Song ,  Sang-Ho Park ,  Ki-Hong Jeong

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A solid-state drive (SSD) includes a main printed circuit board (PCB), and a first semiconductor package and a second semiconductor package respectively mounted on a top surface and a bottom surface of the main PCB. Each of the first and second semiconductor packages has a surface on which connection pads corresponding to a package ball map are disposed. The package ball map includes cells arranged in a plurality of rows and a plurality of columns, and one signal corresponds to each of the cells of the package ball map. The package ball map includes first signals corresponding to at least some of cells included in a selected reference column from among the plurality of columns, and at least one pair of second signals respectively corresponding to cells that are symmetrical to each other with respect to the reference column. The pair of second signals are swappable signals, and the first signals are not swappable signals.

公开(公告)号：US20180233448A1

公开(公告)日：2018-08-16

申请号：US15951925

申请日：2018-04-12

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed

IPC: H01L23/522 ,  H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/56 ,  H05K3/40

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76877 ,  H01L21/76892 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45565 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45669 ,  H01L2224/4569 ,  H01L2224/48 ,  H01L2224/49 ,  H01L2224/73267 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/182 ,  H01L2924/191 ,  H01L2924/19107 ,  H05K3/4046 ,  H05K2201/10287 ,  H05K2203/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/01049

Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.