公开(公告)号：US20180049323A1

公开(公告)日：2018-02-15

申请号：US15792634

申请日：2017-10-24

Applicant: Renesas Electronics Corporation

Inventor： Takafumi BETSUI

IPC: H05K1/18 ,  H05K1/02 ,  H01L23/495 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/182 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49589 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/183 ,  H05K1/185 ,  H05K3/301 ,  H05K3/429 ,  H05K3/4611 ,  H05K3/4697

Abstract: A semiconductor integrated circuit device includes a component built-in board in which at least a first core layer on which a first electronic component is mounted, a second core layer on which a second electronic component is mounted, an adhesive layer arranged between the first core layer and the second core layer, and wiring layers are stacked; a third electronic component mounted in a first core layer side of the component built-in board and electrically connected to the at least one of the first and second electronic components through the wiring layers; and an external connection terminal formed in a second core layer side of the component built-in board and electrically connected to at least one of the first and second electronic components.

公开(公告)号：US20150036406A1

公开(公告)日：2015-02-05

申请号：US14519967

申请日：2014-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US20140284818A1

公开(公告)日：2014-09-25

申请号：US14294978

申请日：2014-06-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi ABEMATSU ,  Takafumi BETSUI ,  Atsushi KURODA

IPC: H01L23/00 ,  H01L23/12

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/04 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.

公开(公告)号：US20140160826A1

公开(公告)日：2014-06-12

申请号：US14182821

申请日：2014-02-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI ,  Naoto TAOKA ,  Motoo SUWA ,  Shigezumi MATSUI ,  Norihiko SUGITA ,  Yoshiharu FUKUSHIMA

IPC: G11C5/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US20210134771A1

公开(公告)日：2021-05-06

申请号：US17030712

申请日：2020-09-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi BETSUI

IPC: H01L25/16 ,  H01L23/538 ,  H02M3/155

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

公开(公告)号：US20180090424A1

公开(公告)日：2018-03-29

申请号：US15657689

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Takafumi BETSUI

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor device includes a semiconductor integrated circuit and a substrate. The semiconductor integrated circuit is, for example, a semiconductor chip. The coefficient of thermal expansion is different between the semiconductor integrated circuit and the substrate. The substrate includes a plurality of soldering balls on the opposite surface to the surface where the semiconductor integrated circuit is mounted. The substrate does not have the soldering balls at a position corresponding to at least one side of the fringe of the semiconductor integrated circuit.

公开(公告)号：US20170033070A1

公开(公告)日：2017-02-02

申请号：US15168550

申请日：2016-05-31

Applicant: Renesas Electronics Corporation

Inventor： Takafumi BETSUI ,  Motoo SUWA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

Abstract translation: 可以防止尺寸增大的半导体装置。 半导体器件包括具有第一主表面和与第一主表面相对的第二主表面的半导体芯片和布线基板，半导体芯片的第二主表面安装在该基板上，使得半导体芯片的第二主表面面向第一主表面 布线基板。 在半导体芯片的第二主表面上，布置有与第一电路连接的多个第一端子和与第二电路连接的多个第二端子。 多个第一端子的布置图案和多个第二端子的布置图案包括相同的布置图案。 在从半导体芯片的第一主表面观察第一电路接近第二电路的布线基板的区域中形成向第一电路提供电源电压的电压线。 在第二电路接近第一电路的布线基板的区域中，形成向第二电路供给电源电压的电压线。

公开(公告)号：US20150116968A1

公开(公告)日：2015-04-30

申请号：US14523862

申请日：2014-10-25

Applicant: Renesas Electronics Corporation

Inventor： Jun YAMADA ,  Takafumi BETSUI

IPC: H01L23/00 ,  H05K1/18 ,  H05K1/11 ,  H01L23/538 ,  H05K1/03

CPC classification number: H01L24/33 ,  H01L23/145 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13611 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/335 ,  H01L2224/33515 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15333 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K3/323 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

Abstract translation: 集成了多核处理器的半导体集成电路芯片通常通过FC结合安装在有机布线板上，通过与衬底集成来形成BGA封装。 在这样的结构中，功率消耗增加，因此仅从芯片的周边部供给的功率不足，从而在芯片中心部分也设置电源焊盘。 然而，由于与多个CPU核心等的集成相关联的布线的增加，在芯片的周边部分和中心部分之间出现一部分，其中不能布置电源焊盘。 根据本申请的概要，在诸如BGA等的半导体集成电路器件中，其中将半导体芯片以面朝上的方式安装在诸如多层有机布线板的中介层之上， 第一组金属通孔电极设置在半导体芯片中以向芯电路等提供电源电位，并且第一金属焊盘通过第一导电粘合构件膜互连。

公开(公告)号：US20190006278A1

公开(公告)日：2019-01-03

申请号：US16126931

申请日：2018-09-10

Applicant: Renesas Electronics Corporation

Inventor： Takafumi BETSUI ,  Nobuyuki MORIKOSHI ,  Tetsushi HADA

IPC: H01L23/522 ,  G06F1/32 ,  G06F13/42 ,  H01L23/498 ,  H01L23/00 ,  G06F13/38 ,  H01R13/645 ,  H01R24/58

Abstract: Object is to provide a semiconductor device with fewer malfunctions. The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals. When viewed from the second main surface, second external terminals to be supplied with the first signal and the second signal are arranged closer to the semiconductor chip than second external terminals to be supplied with the first power supply voltage and the second power supply voltage.

公开(公告)号：US20180068971A1

公开(公告)日：2018-03-08

申请号：US15795365

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Takafumi BETSUI ,  Motoo SUWA

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.