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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开

    公开(公告)号：US20190172527A1

    公开(公告)日：2019-06-06

    申请号：US16259390

    申请日：2019-01-28

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC: G11C11/419 ,  G11C17/12 ,  G11C11/417 ,  G11C11/418

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US09830977B2

    公开(公告)日：2017-11-28

    申请号：US15239410

    申请日：2016-08-17

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC: G11C5/14 ,  G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US10304527B2

    公开(公告)日：2019-05-28

    申请号：US15919525

    申请日：2018-03-13

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC: G11C17/12 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    SEMICONDUCTOR DEVICE HAVING IDENTIFICATION INFORMATION GENERATING FUNCTION AND IDENTIFICATION INFORMATION GENERATION METHOD FOR SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE HAVING IDENTIFICATION INFORMATION GENERATING FUNCTION AND IDENTIFICATION INFORMATION GENERATION METHOD FOR SEMICONDUCTOR DEVICE 有权
    具有识别信息的半导体器件用于半导体器件的生成功能和识别信息生成方法

    公开(公告)号：US20130326243A1

    公开(公告)日：2013-12-05

    申请号：US13903535

    申请日：2013-05-28

    Applicant: Renesas Electronics Corporation

    Inventor： Masanori ISODA ,  Hidehiro Fujiwara ,  Koji Nll

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G06F11/2247 ,  G06F12/14 ,  G06F21/44 ,  G06F21/71 ,  G06F21/78 ,  G06F2212/1052 ,  G11C5/14 ,  G11C8/20 ,  G11C11/417

    Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

    Abstract translation: 一种半导体器件包括具有其输出电压由控制信号控制的电源控制电路的识别信息产生电路和具有第一单元电力线和第二单元电力线的存储器阵列。 当控制信号处于第一状态时，电源控制电路分别向第一单元电力线和第二电力线输出第一电源电压和第二电源电压，并将中间电压输出到第一单元电力线 以及当控制信号处于第二状态时的第二单元电力线。

    Semiconductor integrated circuit device
    8.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US10580484B2

    公开(公告)日：2020-03-03

    申请号：US16259390

    申请日：2019-01-28

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC: G11C7/10 ,  G11C11/419 ,  G11C11/418 ,  G11C17/12 ,  G11C11/417

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US10229733B2

    公开(公告)日：2019-03-12

    申请号：US15919525

    申请日：2018-03-13

    Applicant: Renesas Electronics Corporation

    Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

    IPC: G11C17/12 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

    Semiconductor device including negative bias voltage generation circuit
    10.
    发明授权
    Semiconductor device including negative bias voltage generation circuit 有权
    包括负偏压生成电路的半导体装置

    公开(公告)号：US09171595B2

    公开(公告)日：2015-10-27

    申请号：US13935815

    申请日：2013-07-05

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Hidehiro Fujiwara

    IPC: G11C7/12 ,  G11C11/41 ,  G11C11/4074 ,  G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/41

    Abstract: A semiconductor device includes a bit line connected to memory cells, a negative bias voltage generation circuit generating a negative bias voltage that is to be applied to the bit line during writing, and a negative bias reference voltage generation unit generating a negative bias reference voltage based on a resistance ratio between a first resistor and a second resistor.

    Abstract translation: 半导体器件包括连接到存储单元的位线，产生在写入期间施加到位线的负偏置电压的负偏置电压产生电路和产生基于负偏置基准电压的负偏置基准电压产生单元 基于第一电阻器和第二电阻器之间的电阻比。

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