公开(公告)号：US10825814B2

公开(公告)日：2020-11-03

申请号：US16287570

申请日：2019-02-27

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Yuichiro Ishii

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

公开(公告)号：US10706917B2

公开(公告)日：2020-07-07

申请号：US16176299

申请日：2018-10-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji Nii ,  Yuichiro Ishii ,  Yohei Sawada ,  Makoto Yabuuchi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12

Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.

公开(公告)号：US10672463B2

公开(公告)日：2020-06-02

申请号：US16248489

申请日：2019-01-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi

IPC: G11C5/06 ,  G11C11/419

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

公开(公告)号：US10566329B2

公开(公告)日：2020-02-18

申请号：US15925762

申请日：2018-03-19

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi

IPC: G11C5/06 ,  H01L27/088 ,  G11C7/10 ,  H01L27/02 ,  H01L27/06 ,  G11C7/22

Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

公开(公告)号：US10460795B2

公开(公告)日：2019-10-29

申请号：US16214220

申请日：2018-12-10

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Makoto Yabuuchi ,  Masao Morimoto

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C8/08 ,  G11C8/06

Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.

公开(公告)号：US20190172527A1

公开(公告)日：2019-06-06

申请号：US16259390

申请日：2019-01-28

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

IPC: G11C11/419 ,  G11C17/12 ,  G11C11/417 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.

公开(公告)号：US10068891B2

公开(公告)日：2018-09-04

申请号：US15719830

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Takeshi Okagaki ,  Koji Shibutani ,  Makoto Yabuuchi ,  Nobuhiro Tsuda

IPC: H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L29/417

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

公开(公告)号：US20180240514A1

公开(公告)日：2018-08-23

申请号：US15957803

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

公开(公告)号：US10002662B2

公开(公告)日：2018-06-19

申请号：US15716639

申请日：2017-09-27

Applicant: Renesas Electronics Corporation

Inventor： Shinji Tanaka ,  Makoto Yabuuchi ,  Yuta Yoshida

IPC: G11C5/06 ,  G11C11/419 ,  G11C11/418 ,  G11C7/22 ,  G11C7/08 ,  G11C11/415 ,  G11C8/10 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

公开(公告)号：US09947393B2

公开(公告)日：2018-04-17

申请号：US15797135

申请日：2017-10-30

Applicant: Renesas Electronics Corporation

Inventor： Makoto Yabuuchi ,  Hidehiro Fujiwara

IPC: G11C7/10 ,  G11C11/419 ,  G11C17/12 ,  G11C11/418 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

Abstract: A semiconductor integrated circuit device includes a control unit which causes a column selection circuit to separate bit line pairs from a common bit line pair and causes a sense amplifier circuit to amplify a potential difference between the common bit line pair precharged by a precharge circuit, in response to a unique ID generation instruction.