中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.014 seconds)

    Semiconductor device and method of manufacturing the same
    4.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US09356135B2

    公开(公告)日：2016-05-31

    申请号：US14605027

    申请日：2015-01-26

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kosuke Yoshida ,  Tetsuya Nitta

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/7813 ,  H01L27/0922 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7809

    Abstract: To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same.In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.

    Abstract translation: 为了提供能够通过抑制双重RESURF结构的尺寸变化来抑制击穿电压降低的半导体器件及其制造方法。 在半导体器件中，上部RESURF区域形成为与半导体衬底内的一个主表面侧的第一掩埋区域接触。 半导体衬底具有形成为在一个主表面上到达上RESURF区域的场氧化物。 半导体衬底包括形成为与一个主表面侧上部RESURF区接触并与半导体衬底内的场氧化物相邻的第二导电类型体区。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160181357A1

    公开(公告)日：2016-06-23

    申请号：US14403225

    申请日：2014-01-27

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

    IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

    Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (Si) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

    Abstract translation: 在半导体装置中，在n +源极区域（SR）的第一和第二部分（P1，P2）之间的主表面（Si）中布置有p +背栅极区域（PBG），并且配置在靠近n + 漏极区域（DR）相对于n +源极区域（SR）。 由此，可以获得具有高导通状态击穿电压的半导体器件。

Patent Agency Ranking