公开(公告)号：US09437644B2

公开(公告)日：2016-09-06

申请号：US14528724

申请日：2014-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Hiroyuki Arie

IPC: H01L27/146 ,  H01L31/028 ,  H01L31/18

CPC classification number: H01L27/14645 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/028 ,  H01L31/103 ,  H01L31/1804

Abstract: To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.

Abstract translation: 为了提供具有高灵敏度的光电转换元件的半导体器件，引起较少的起霜，并且能够提供高可靠性的图像。 半导体器件具有半导体衬底，第一p型外延层，第二p型外延层和第一光电转换元件。 第一p型外延层形成在半导体衬底的主表面上。 形成第二p型外延层以覆盖第一p型外延层的上表面。 第一光电转换元件形成在第二p型外延层中。 第一和第二p型外延层各自由硅制成，并且第一p型外延层的p型杂质浓度高于第二p型外延层的p型杂质浓度。

公开(公告)号：US09755094B2

公开(公告)日：2017-09-05

申请号：US14948190

申请日：2015-11-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi Sakai ,  Katsumi Eikyu

IPC: H01L27/146 ,  H01L31/0352 ,  H01L31/103

CPC classification number: H01L31/03529 ,  H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/103 ,  Y02E10/50

Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity.In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

公开(公告)号：US11362207B2

公开(公告)日：2022-06-14

申请号：US17095241

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi Sakai ,  Satoru Tokuda ,  Ryuuji Umemoto ,  Katsumi Eikyu ,  Hiroshi Yanagigawa

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

公开(公告)号：US10249708B2

公开(公告)日：2019-04-02

申请号：US15727400

申请日：2017-10-06

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

公开(公告)号：US10121894B2

公开(公告)日：2018-11-06

申请号：US15649984

申请日：2017-07-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/10

Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

公开(公告)号：US20180033855A1

公开(公告)日：2018-02-01

申请号：US15727400

申请日：2017-10-06

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

公开(公告)号：US09806147B2

公开(公告)日：2017-10-31

申请号：US14403225

申请日：2014-01-27

Applicant: Renesas Electronics Corporation

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

公开(公告)号：US12159934B2

公开(公告)日：2024-12-03

申请号：US17722788

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsumi Eikyu ,  Atsushi Sakai ,  Yotaro Goto

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

公开(公告)号：US10910492B2

公开(公告)日：2021-02-02

申请号：US16036489

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Hiroki Fujii ,  Atsushi Sakai ,  Takahiro Mori

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/732

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

公开(公告)号：US20160181357A1

公开(公告)日：2016-06-23

申请号：US14403225

申请日：2014-01-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kosuke Yoshida ,  Tetsuya Nitta ,  Atsushi Sakai

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/7813 ,  H01L29/7816

Abstract: In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (Si) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.

Abstract translation: 在半导体装置中，在n +源极区域（SR）的第一和第二部分（P1，P2）之间的主表面（Si）中布置有p +背栅极区域（PBG），并且配置在靠近n + 漏极区域（DR）相对于n +源极区域（SR）。 由此，可以获得具有高导通状态击穿电压的半导体器件。