公开(公告)号：US20180205225A1

公开(公告)日：2018-07-19

申请号：US15918309

申请日：2018-03-12

Applicant: Renesas Electronics Corporation

Inventor： Masashi ARAKAWA ,  Tadashi FUKUI ,  Koji TAKAYANAGI

IPC: H02H9/04 ,  H01L27/02 ,  H02H9/00

CPC classification number: H02H9/044 ,  H01L27/0285 ,  H02H9/005

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

公开(公告)号：US20150303144A1

公开(公告)日：2015-10-22

申请号：US14590294

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Takeshi IWAMOTO ,  Kazushi KONO ,  Masashi ARAKAWA ,  Toshiaki YONEZU ,  Shigeki OBAYASHI

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract translation: 一种具有电熔丝结构的半导体器件，其接收电流以允许电熔丝被切割而不损坏保险丝周围的部分。 电熔丝可以电连接在电子电路和冗余电路之间作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

公开(公告)号：US20180138121A1

公开(公告)日：2018-05-17

申请号：US15869707

申请日：2018-01-12

Applicant: Renesas Electronics Corporation

Inventor： Takeshi IWAMOTO ,  Kazushi KONO ,  Masashi ARAKAWA ,  Toshiaki YONEZU ,  Shigeki OBAYASHI

IPC: H01L23/525 ,  H01L23/532 ,  H01L23/528 ,  H01H85/041 ,  H01L23/522 ,  H01L23/62

Abstract: A semiconductor device is provided which includes an interlayer dielectric formed on a semiconductor substrate, a first insulating layer, having a trench, formed on the interlayer dielectric, a barrier film formed on side and bottom surfaces of the first trench, an electric fuse formed on the barrier film, a second insulating layer formed to directly contact the electric fuse, and a third insulating layer formed on the second insulating layer. A linear expansion coefficient of the electric fuse is greater than a linear expansion coefficient of the first insulating layer and the second insulating layer, and a melting point of the barrier film is greater than a melting point of the electric fuse.

公开(公告)号：US20170040261A1

公开(公告)日：2017-02-09

申请号：US15298484

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Takeshi IWAMOTO ,  Kazushi KONO ,  Masashi ARAKAWA ,  Toshiaki YONEZU ,  Shigeki OBAYASHI

IPC: H01L23/525 ,  H01L23/528 ,  H01L23/532 ,  H01H85/041

CPC classification number: H01L23/5256 ,  H01H85/041 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract translation: 一种具有电熔丝结构的半导体器件，其接收电流以允许电熔丝被切割而不损坏保险丝周围的部分。 电熔丝可以电连接在电子电路和冗余电路之间作为电子电路的备用电路。 在这些电路用树脂密封之后，可以通过从外部接收电流来切断保险丝。 电熔丝形成为细层，由主配线和阻挡膜构成。 主布线和阻挡膜中的每一个的线膨胀系数大于每个绝缘体层的线膨胀系数。 主配线和阻挡膜中的每一个的熔点低于每个绝缘体层的熔点。

公开(公告)号：US20160094027A1

公开(公告)日：2016-03-31

申请号：US14865418

申请日：2015-09-25

Applicant: Renesas Electronics Corporation

Inventor： Masashi ARAKAWA ,  Tadashi FUKUI ,  Koji TAKAYANAGI

IPC: H02H9/04 ,  H02H9/00

CPC classification number: H02H9/044 ,  H01L27/0285 ,  H02H9/005

Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. Agate width of the second transistor is narrower than a gate width of the first transistor.

Abstract translation: 提供了可以在保持ESD电阻的同时促进面积减小的半导体器件。 半导体器件包括电源线，接地线和设置在电源线和接地线之间的保护电路，以便应对静电放电。 保护电路包括第一晶体管，第一电阻元件，第二晶体管，第一电容元件，第一反相器和保护晶体管。 第二晶体管的玛瑙宽度窄于第一晶体管的栅极宽度。

公开(公告)号：US20160071572A1

公开(公告)日：2016-03-10

申请号：US14942130

申请日：2015-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Natsuki IKEHATA ,  Kazuo TANAKA ,  Takeo TOBA ,  Masashi ARAKAWA

IPC: G11C11/4091 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

Abstract: An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

Abstract translation: 差分放大电路的输出信号特性得到改善。 当输入数据信号变为“低”时，流过第一晶体管的电流将减小，并且第一电阻和第二电阻之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为“高”时，第一晶体管的电流增加，因此节点处的电位减小。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。