公开(公告)号：US20130207245A1

公开(公告)日：2013-08-15

申请号：US13765183

申请日：2013-02-12

Applicant: Renesas Electronics Corporation

Inventor： Naoya INOUE ,  Masayoshi TAGAMI

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76825 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/7682 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding.

Abstract translation: 通过CVD在半导体衬底上沉积烷基化的环状硅氧烷前体来制备具有高弹性模量的低k多孔绝缘膜。 在CVD期间或在沉积膜上原位进行CVD的等离子体增强。 膜的UV固化在受控的温度和时间条件下进行，其在相邻环部分之间产生紧密的结合结构，而不破坏Si-O环键合。

公开(公告)号：US20140187047A1

公开(公告)日：2014-07-03

申请号：US14141042

申请日：2013-12-26

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masayoshi TAGAMI ,  Naoya INOUE

IPC: H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method for forming a semiconductor device that includes a SiARC layer formed over a photoresist film which is formed over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer. The SiARC layer has an etch rate substantially similar to the etch rate of the spacer assist layer. The photoresist layer and the SiARC layer are removed from a first region to expose the spacer portions and the spacer assist layer. The SiARC layer in the second region and the exposed spacer assist layer in the first region are simultaneously etched leaving remaining spacer portions and remaining spacer assist layer portions. A part of the hard mask layer is etched to form hard mask portions in the first region using the remaining spacer portions and the remaining spacer assist layer portions as an etching mask.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括在形成在形成在硬掩模层上的间隔辅助层上的间隔部分上形成的光致抗蚀剂膜上形成的SiARC层。 SiARC层具有与间隔辅助层的蚀刻速率基本相似的蚀刻速率。 从第一区域去除光致抗蚀剂层和SiARC层，以露出间隔物部分和间隔辅助层。 第二区域中的SiARC层和第一区域中的暴露的间隔辅助层被同时蚀刻，留下剩余的间隔部分和剩余的间隔辅助层部分。 蚀刻硬膜掩模层的一部分，以使用剩余的间隔物部分和剩余的间隔辅助层部分作为蚀刻掩模在第一区域中形成硬掩模部分。