公开(公告)号：US20200313000A1

公开(公告)日：2020-10-01

申请号：US16753949

申请日：2017-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220406936A1

公开(公告)日：2022-12-22

申请号：US17897844

申请日：2022-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO ,  Shiro KAMOHARA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.