公开(公告)号：US20160079426A1

公开(公告)日：2016-03-17

申请号：US14952782

申请日：2015-11-25

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Hiroshi TAKEDA ,  Toshiharu NAGUMO ,  Takashi HASE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/40 ,  H01L29/20

CPC classification number: H01L29/7849 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66522 ,  H01L29/66659 ,  H01L29/7835

Abstract: To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

公开(公告)号：US20160049375A1

公开(公告)日：2016-02-18

申请号：US14925584

申请日：2015-10-28

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Takashi ONIZAWA ,  Takashi HASE ,  Shigeru HIRAO ,  Tadatoshi DANNO

IPC: H01L23/00 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3178 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.

Abstract translation: 半导体器件包括包括第一面的衬底。 该器件还包括缓冲层，半导体层，源极和漏极以及栅电极。 在半导体层上形成沟槽，使得沟槽在平面图中围绕源电极，漏电极和栅电极，沟槽穿过半导体层和缓冲层，并且沟槽的底部到达 至少衬底的内部。 从衬底的第一面到沟槽的底部的距离在衬底的厚度方向上为100nm以上。

公开(公告)号：US20190187737A1

公开(公告)日：2019-06-20

申请号：US16173576

申请日：2018-10-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masaharu MATSUDAIRA ,  Takashi HASE ,  Akira TANABE ,  Kazuya UEJIMA

IPC: G05F3/20 ,  G05F3/24 ,  G01K7/01

CPC classification number: G05F3/205 ,  G01K7/01 ,  G05F3/245 ,  H03K17/145 ,  H03K2217/0018

Abstract: There is a need to ensure operations at a predetermined operating frequency when a temperature changes in an operating state. A semiconductor device includes: a bias-applied portion applied with a substrate bias; a temperature sensor to detect a temperature; and a substrate bias generator to apply the bias-applied portion with a substrate bias corresponding to the temperature detected by the temperature sensor. The bias-applied portion, while applied with a substrate bias by the substrate bias generator, shifts between an operating state and a stopped state. The substrate bias generator applies the bias-applied portion with a substrate bias configured so as not to cause an upper limit of an operating frequency for the bias-applied portion to be smaller than a predetermined value under condition of the temperature detected by the temperature sensor.

公开(公告)号：US20240363750A1

公开(公告)日：2024-10-31

申请号：US18771200

申请日：2024-07-12

Applicant: Renesas Electronics Corporation

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/517 ,  H03F3/45179

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20220406936A1

公开(公告)日：2022-12-22

申请号：US17897844

申请日：2022-08-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO ,  Shiro KAMOHARA

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20180069051A1

公开(公告)日：2018-03-08

申请号：US15697203

申请日：2017-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto UEKI ,  Takashi HASE

IPC: H01L27/24 ,  H01L27/10 ,  H01L43/12 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/101 ,  H01L27/2436 ,  H01L43/12 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/1633

Abstract: A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

公开(公告)号：US20160365144A1

公开(公告)日：2016-12-15

申请号：US15099660

申请日：2016-04-15

Applicant: Renesas Electronics Corporation

Inventor： Makoto UEKI ,  Koji MASUZAKI ,  Masaharu MATSUDAIRA ,  Takashi HASE ,  Yoshihiro HAYASHI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.

Abstract translation: 包括各自包括电阻变化元件和控制电路的存储单元。 该电路执行On写入处理，以将存储单元中的On写入脉冲施加在电阻变化元件的电阻值低于第一基准值的电阻状态，以及用于 对具有第二参考值或更高的高电阻状态的ON写入脉冲施加具有相反极性的OFF写入脉冲。 该电路在On写入处理中应用与On写入脉冲具有相同极性的试用脉冲，其脉冲宽度短于On写入脉冲的脉冲宽度，并且具有与On 写入脉冲，按此顺序将“写入”脉冲应用于单元格。

公开(公告)号：US20160276026A1

公开(公告)日：2016-09-22

申请号：US14962777

申请日：2015-12-08

Applicant: Renesas Electronics Corporation

Inventor： Takashi HASE ,  Naoya FURUTAKE ,  Koji MASUZAKI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: When writing ReRAM cells, it is pursued to set the cells in a sufficiently high or low resistance state, while preventing excessive writing. Disclosed is a semiconductor storage device including memory cells, each including a variable resistance element, and control circuitry that executes an Off writing process of applying Off writing pulse to a memory cell to turn it into high resistance state and an On writing process of applying On writing pulse to turn it into low resistance state. The control circuitry, when the memory cell is placed in low resistance state, after applying Off writing pulse, applies a reading pulse for a verify process of reading whether it is placed in high or low resistance state. If the memory cell is not placed in high resistance state as a result of the verify process, the control circuitry applies a reset pulse comprising On writing pulse, applies Off writing pulse with extended pulse width and executes the verify process in mentioned order.

Abstract translation: 当写入ReRAM单元时，追求将单元设置在足够高或低电阻状态，同时防止过度写入。 公开了一种包括存储单元的半导体存储装置，每个存储单元包括可变电阻元件，以及控制电路，其执行将写入脉冲施加到存储器单元以将其变为高电阻状态的关闭写入处理以及应用于On 写入脉冲将其变为低电阻状态。 当存储单元置于低电阻状态时，控制电路在施加关闭写入脉冲之后，施加读取脉冲以进行读取的验证处理是否处于高电平或低电阻状态。 如果作为验证处理的结果，存储单元未被置于高电阻状态，则控制电路施加包括在写入脉冲中的复位脉冲，施加具有扩展脉冲宽度的关闭写入脉冲，并按照上述顺序执行验证处理。

公开(公告)号：US20200313000A1

公开(公告)日：2020-10-01

申请号：US16753949

申请日：2017-11-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuya UEJIMA ,  Shiro KAMOHARA ,  Michio ONDA ,  Takashi HASE ,  Tatsuo NISHINO

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/51 ,  H03F3/45

Abstract: In a semiconductor device according to an embodiment, a thickness of a semiconductor layer of an SOI substrate on which a field effect transistor constituting an analog circuit is formed is set to 2 nm or more and 24 nm or less.

公开(公告)号：US20170309336A1

公开(公告)日：2017-10-26

申请号：US15646933

申请日：2017-07-11

Applicant: Renesas Electronics Corporation

Inventor： Takashi HASE ,  Naoya FURUTAKE ,  Koji MASUZAKI

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79 ,  G11C2213/82

Abstract: A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first writing process of applying a first writing pulse to a memory cell to turn the memory cell state into a first resistance state and a second writing process of applying a second writing pulse of opposite polarity to the first writing pulse to turn the memory cell into a second resistance state, the memory cell from among the plurality of memory cells. The control circuitry, when the memory cell is placed in the second resistance state, after applying the first writing pulse to the memory cell, applies a reading pulse for a verify process of reading whether the variable resistance element is placed in the first resistance state or the second resistance state.