公开(公告)号：US20150255564A1

公开(公告)日：2015-09-10

申请号：US14717292

申请日：2015-05-20

Applicant: Renesas Electronics Corporation

Inventor： Takahiro TOMIMATSU

IPC: H01L29/51 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78

Abstract: Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed.

Abstract translation: 在半导体衬底上形成包括界面层，HfON膜和HfSiON膜的栅极绝缘膜。 然后，在HfSiON膜上形成含Al膜和掩模层。 随后，从n沟道MISFET形成区域选择性地去除掩模层和含Al膜。 然后，在n沟道MISFET形成区域中的HfSiON膜上并且在p沟道MISFET形成区域中的掩模层之上形成含稀土元素的膜。 进行热处理以在n沟道MISFET形成区域中引起HfON膜和HfSiON膜和含稀土元素的膜之间的反应，并引起HfON膜和HfSiON膜中的每一个之间的反应 以及p沟道MISFET形成区域中的含Al膜。 此后，除去未反应的含稀土元素膜和掩模层，然后形成金属栅电极。

公开(公告)号：US20140070288A1

公开(公告)日：2014-03-13

申请号：US14024117

申请日：2013-09-11

Applicant: Renesas Electronics Corporation

Inventor： Takahiro TOMIMATSU ,  Takeshi KAMINO ,  Takeshi KAWAMURA

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14612 ,  H01L27/14629 ,  H01L27/14643 ,  H01L27/14685

Abstract: To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall.

Abstract translation: 为了防止由于波导和光电二极管之间的距离的变化引起的像素部分的灵敏度的劣化以及由于抑制入射光的反射而导致的光衰减。 在像素区域中，形成穿过第四层间绝缘膜等并到达侧壁绝缘膜的波导。 侧壁绝缘膜被配置为具有氧化硅膜和氮化硅膜的堆叠结构。 波导形成为穿透侧壁绝缘膜的氮化硅膜，并到达侧壁绝缘膜的氧化硅膜，或者到达侧壁的氮化硅膜。

公开(公告)号：US20170229504A1

公开(公告)日：2017-08-10

申请号：US15499132

申请日：2017-04-27

Applicant: Renesas Electronics Corporation

Inventor： Takahiro TOMIMATSU

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689

Abstract: A gate electrode of a field effect transistor is formed. Next, an offset spacer film with a double-layer structure including a silicon oxide film as a lower-layer film and a silicon nitride film as an upper-layer film is formed on a sidewall surface of the gate electrode. The silicon nitride film serves as a supply source of an element for terminating dangling bonds of silicon in a device formation region. Next, treatment for leaving the offset spacer film intact or treatment for removing the silicon nitride film of the offset spacer film is performed. Thereafter, a sidewall insulating film is formed on the sidewall surface of the gate electrode.

公开(公告)号：US20170040360A1

公开(公告)日：2017-02-09

申请号：US15200803

申请日：2016-07-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji IIZUKA ,  Takahiro TOMIMATSU

IPC: H01L27/146

CPC classification number: H01L27/14605 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/1463 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/14698

Abstract: An imaging device is provided, in which the dynamic range of still pictures can be suppressed from being decreased. In the imaging device, a photodiode including an n-type impurity region and a photodiode including an n-type impurity region are formed in a p-type well. An n-type impurity region is formed between the n-type impurity region on one side and that on the other side so as to contact each of the two. The impurity concentration of the last-formed n-type impurity region is set to be lower than those of the first-formed n-type impurity regions.

Abstract translation: 提供一种成像装置，其中可以抑制静止图像的动态范围的减小。 在成像装置中，在p型阱中形成包括n型杂质区域的光电二极管和包含n型杂质区域的光电二极管。 在一侧的n型杂质区域和另一侧的n型杂质区域之间形成n型杂质区域，以接触两者之中的每一个。 最后形成的n型杂质区域的杂质浓度设定为低于第一形成的n型杂质区域的杂质浓度。

公开(公告)号：US20160111456A1

公开(公告)日：2016-04-21

申请号：US14894298

申请日：2013-06-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro TOMIMATSU

IPC: H01L27/146

CPC classification number: H01L27/14614 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689

Abstract: A gate electrode of a field effect transistor is formed. Next, an offset spacer film with a double-layer structure including a silicon oxide film as a lower-layer film and a silicon nitride film as an upper-layer film is formed on a sidewall surface of the gate electrode. The silicon nitride film serves as a supply source of an element for terminating dangling bonds of silicon in a device formation region. Next, treatment for leaving the offset spacer film intact or treatment for removing the silicon nitride film of the offset spacer film is performed. Thereafter, a sidewall insulating film is formed on the sidewall surface of the gate electrode.

Abstract translation: 形成场效应晶体管的栅电极。 接下来，在栅电极的侧壁表面上形成具有包括作为下层膜的氧化硅膜和作为上层膜的氮化硅膜的双层结构的偏移间隔膜。 氮化硅膜用作在器件形成区域中终止硅的悬挂键的元件的供给源。 接下来，进行用于离开偏移间隔膜的处理或用于去除偏移间隔膜的氮化硅膜的处理。 此后，在栅电极的侧壁表面上形成侧壁绝缘膜。

公开(公告)号：US20160079294A1

公开(公告)日：2016-03-17

申请号：US14948713

申请日：2015-11-23

Applicant: Renesas Electronics Corporation

Inventor： Takahiro TOMIMATSU ,  Takeshi KAMINO ,  Takeshi KAWAMURA

IPC: H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14612 ,  H01L27/14629 ,  H01L27/14643 ,  H01L27/14685

Abstract: To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall.

Abstract translation: 为了防止由于波导和光电二极管之间的距离的变化引起的像素部分的灵敏度的劣化以及由于抑制入射光的反射而导致的光衰减。 在像素区域中，形成穿过第四层间绝缘膜等并到达侧壁绝缘膜的波导。 侧壁绝缘膜被配置为具有氧化硅膜和氮化硅膜的堆叠结构。 波导形成为穿透侧壁绝缘膜的氮化硅膜，并到达侧壁绝缘膜的氧化硅膜，或者到达侧壁的氮化硅膜。

公开(公告)号：US20130207203A1

公开(公告)日：2013-08-15

申请号：US13740783

申请日：2013-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takahiro TOMIMATSU

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/513 ,  H01L21/28185 ,  H01L21/823857 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/78

Abstract: Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed.

Abstract translation: 在半导体衬底上形成包括界面层，HfON膜和HfSiON膜的栅极绝缘膜。 然后，在HfSiON膜上形成含Al膜和掩模层。 随后，从n沟道MISFET形成区域选择性地去除掩模层和含Al膜。 然后，在n沟道MISFET形成区域中的HfSiON膜上并且在p沟道MISFET形成区域中的掩模层之上形成含稀土元素的膜。 进行热处理以在n沟道MISFET形成区域中引起HfON膜和HfSiON膜和含稀土元素的膜之间的反应，并引起HfON膜和HfSiON膜中的每一个之间的反应 以及p沟道MISFET形成区域中的含Al膜。 此后，除去未反应的含稀土元素膜和掩模层，然后形成金属栅电极。