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公开(公告)号：US20190260363A1
公开(公告)日：2019-08-22
申请号：US16248372
申请日：2019-01-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yoji KASHIHARA , Koichi TAKEDA
Abstract: To stably operate a negative-voltage level shifter even when a voltage value of a high level of an input signal is lowered, a negative-voltage level shifter in a semiconductor device includes a first level shifter, a second level shifter, and a first medium-voltage generating circuit. The first level shifter converts a high level of an input signal from a positive first power-supply voltage to a first medium voltage. The second level shifter converts a low level of an output signal of the first level shifter from a third power-supply voltage to a negative fourth power-supply voltage that is lower than the third power-supply voltage. The first medium-voltage generating circuit generates the first medium voltage in such a manner that the first medium voltage is higher than the first power-supply voltage and is lower than a second power-supply voltage, and includes a source-follower NMOS transistor and a clamping PMOS transistor.
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Patent Agency Ranking
公开(公告)号：US20160225453A1
公开(公告)日：2016-08-04
申请号：US14961643
申请日：2015-12-07
Applicant: Renesas Electronics Corporation
Inventor： Yoji KASHIHARA
Abstract: The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.
Abstract translation: 在非易失性存储器的解码电路中减少了电平移位器的数量。 半导体器件配置有电可重写非易失性存储单元阵列，以及产生选择信号以选择存储器栅极线（字线）的驱动器的解码电路。 解码电路包括电平移位器，用于在预解码之后升高信号。 通过解码由逻辑运算电路中的电平移位器升压的预解码信号来生成选择信号。 在每个电平移位器的前级提供了用于根据操作模式反转预解码信号的逻辑电平的逻辑门。 当解码升压预解码信号时，逻辑运算电路根据操作模式执行不同的逻辑运算。
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公开(公告)号：US20190260362A1
公开(公告)日：2019-08-22
申请号：US16248307
申请日：2019-01-15
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yoji KASHIHARA
Abstract: Provided is a level shifter which can retain an operation margin and enhance an exceeded-breakdown-voltage preventing effect. The level shifter in an embodiment includes an exceeded-breakdown-voltage prevention circuit between a pair of first-conductivity-type cross-coupled transistors and a pair of second-conductivity-type input transistors. The exceeded-breakdown-voltage prevention circuit includes first-conductivity-type first transistors and second-conductivity-type second transistors which are coupled in series to each other, and first-conductivity-type third transistors coupled in series to the first and second transistors on a higher-potential side.
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公开(公告)号：US20190259455A1
公开(公告)日：2019-08-22
申请号：US16250324
申请日：2019-01-17
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yoji KASHIHARA
Abstract: A semiconductor device includes first and second voltage control lines for a first memory block and third and fourth voltage control lines for a second memory block, for driving gate lines for memory transistors; a first decoder driving the first and third voltage control lines; a second decoder driving the second and fourth voltage control lines; and a control circuit controlling a voltage for the first and second decoders. The control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and a third voltage between the first and second voltages, and the second voltage to the second decoder, before writing operation; and supplies the first voltage and the third voltage to the first decoder and a fourth voltage between the third and second voltages, and a fifth voltage lower than the second voltage to the second decoder, in the writing operation.
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公开(公告)号：US20190088344A1
公开(公告)日：2019-03-21
申请号：US16048392
申请日：2018-07-30
Applicant: Renesas Electronics Corporation
Inventor： Yoji KASHIHARA
CPC classification number: G11C16/3459 , G11C16/0408 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3445
Abstract: To reduce a time required for verify processing of a semiconductor storage device, a semiconductor storage device according to one embodiment includes a plurality of unit memory arrays each including a plurality of memory blocks, a sense amplifier, and a verify circuit. When the semiconductor storage device performs verify processing, a pulse corresponding to verify data is applied to each memory cell of each memory block, and an expectation value corresponding to the verify data is set to each verify circuit. Each verify circuit performs the verify processing by comparing data stored read by the sense amplifier with the expectation value.
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公开(公告)号：US20170206971A1
公开(公告)日：2017-07-20
申请号：US15326329
申请日：2014-08-14
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Yoji KASHIHARA
CPC classification number: G11C16/24 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/14 , G11C16/3427
Abstract: A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality of split type memory cells (250R), a first control gate line (CGL) connected to a control gate (CG) of a split type memory cell (100L), and a second control gate line (CGR) connected to a control gate (CG) of a split type memory cell (100R). The semiconductor device further includes a first memory gate line (MGL) connected to a memory gate (MG) of the split type memory cell (100L), and a second memory gate line (MGR) connected to a memory gate (MG) of the split type memory cell (100R).
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